专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090282303A1 BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM 有权
标题翻译：用可测试的测试程序构建测试控制器
公开(公告)号：US20090282303A1
公开(公告)日：2009-11-12
申请号：US12118477
申请日：2008-05-09
申请人： Alexandre Andreev , Anatoli A. Bolotov
发明人： Alexandre Andreev , Anatoli A. Bolotov
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G11C5/04 , G11C29/16 , G11C2029/0401
摘要： An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.
摘要翻译：一种包括处理器和内部存储器的装置。处理器可以被配置为使用（i）网表和（ii）测试程序来测试外部存储器。内部存储器可以被配置为存储测试程序。测试程序可以独立于存储网表而被下载到内部存储器。

22. 发明申请

US20120278775A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20120278775A1
公开(公告)日：2012-11-01
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

23. 发明授权

US08176397B2 Variable redundancy reed-solomon encoder 失效
标题翻译：可变冗余雷达独奏编码器
公开(公告)号：US08176397B2
公开(公告)日：2012-05-08
申请号：US12211985
申请日：2008-09-17
申请人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
发明人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
IPC分类号： G06F11/00
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

24. 发明授权

US08046643B2 Transport subsystem for an MBIST chain architecture 失效
标题翻译：用于MBIST链架构的传输子系统
公开(公告)号：US08046643B2
公开(公告)日：2011-10-25
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括：控制器，被配置为呈现一个或多个命令并接收一个或多个响应;多个传输电路，被配置为接收命令中的一个，呈现响应，并产生一个或多个控制信号;以及多个存储器 - 控制电路，每个耦合到所述多个传输电路中的相应一个，并被配置为响应于所述一个或多个控制信号而产生一个或多个存储器访问信号，响应于所述控制电路响应于所述控制电路接收来自相应存储器的一个或多个存储器输出信号一个或多个存储器访问信号，并且响应于一个或多个存储器输出信号而产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

25. 发明申请

US20100070831A1 VARIABLE REDUNDANCY REED-SOLOMON ENCODER 失效
标题翻译：可变冗余冗余编码器
公开(公告)号：US20100070831A1
公开(公告)日：2010-03-18
申请号：US12211985
申请日：2008-09-17
申请人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
发明人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
IPC分类号： H03M13/15 , G06F11/07
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

26. 发明授权

US07584442B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

27. 发明申请

US20070113212A1 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

28. 发明授权

US08245168B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08245168B2
公开(公告)日：2012-08-14
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

29. 发明授权

US08209589B2 Reed-solomon decoder with a variable number of correctable errors 失效
标题翻译： Reed-solomon解码器具有可变数量的可纠正错误
公开(公告)号：US08209589B2
公开(公告)日：2012-06-26
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

30. 发明申请

US20100070832A1 REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS 失效
标题翻译： REED-SOLOMON解码器具有可变数量的可纠正错误
公开(公告)号：US20100070832A1
公开(公告)日：2010-03-18
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式