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21. 发明授权

US08176397B2 Variable redundancy reed-solomon encoder 失效
标题翻译：可变冗余雷达独奏编码器
公开(公告)号：US08176397B2
公开(公告)日：2012-05-08
申请号：US12211985
申请日：2008-09-17
申请人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
发明人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
IPC分类号： G06F11/00
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

22. 发明申请

US20100070831A1 VARIABLE REDUNDANCY REED-SOLOMON ENCODER 失效
标题翻译：可变冗余冗余编码器
公开(公告)号：US20100070831A1
公开(公告)日：2010-03-18
申请号：US12211985
申请日：2008-09-17
申请人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
发明人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
IPC分类号： H03M13/15 , G06F11/07
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

23. 发明授权

US07584442B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

24. 发明申请

US20070113212A1 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

25. 发明申请

US20060104145A1 Memory tiling architecture 有权
标题翻译：记忆瓷砖结构
公开(公告)号：US20060104145A1
公开(公告)日：2006-05-18
申请号：US10990237
申请日：2004-11-16
申请人： Alexandre Andreev , Igor Vikhliantsev , Ivan Pavisic
发明人： Alexandre Andreev , Igor Vikhliantsev , Ivan Pavisic
IPC分类号： G11C8/00
CPC分类号： G06F17/5045
摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.
摘要翻译：将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。

26. 发明授权

US08245168B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08245168B2
公开(公告)日：2012-08-14
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

27. 发明授权

US08209589B2 Reed-solomon decoder with a variable number of correctable errors 失效
标题翻译： Reed-solomon解码器具有可变数量的可纠正错误
公开(公告)号：US08209589B2
公开(公告)日：2012-06-26
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

28. 发明申请

US20100070832A1 REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS 失效
标题翻译： REED-SOLOMON解码器具有可变数量的可纠正错误
公开(公告)号：US20100070832A1
公开(公告)日：2010-03-18
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

29. 发明申请

US20080295044A1 METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：将设计记忆映射到集成电路布局的方法和装置
公开(公告)号：US20080295044A1
公开(公告)日：2008-11-27
申请号：US12186159
申请日：2008-08-05
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

30. 发明授权

US07424687B2 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US07424687B2
公开(公告)日：2008-09-09
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

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