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21. 发明授权

US5468983A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5468983A
公开(公告)日：1995-11-21
申请号：US203627
申请日：1994-03-01
申请人： Junji Hirase , Shin Hashimoto
发明人： Junji Hirase , Shin Hashimoto
IPC分类号： H01L27/105 , H01L27/108 , H01L29/78 , H01L33/00
CPC分类号： H01L27/108 , H01L27/105
摘要： In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.
摘要翻译：在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。在集成电路区域中，设置多个单元形成区，分别由隔离限定。每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。所有虚拟细胞可能是缺乏伪细胞的P-N。因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

22. 发明申请

US20080258229A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080258229A1
公开(公告)日：2008-10-23
申请号：US12028392
申请日：2008-02-08
申请人： Hiroshi OHKAWA , Junji Hirase , Hisashi Ogawa , Kenji Yoneda
发明人： Hiroshi OHKAWA , Junji Hirase , Hisashi Ogawa , Kenji Yoneda
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L27/092 , H01L27/0922 , H01L29/518
摘要： A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the second gate insulating film are made of silicon oxynitride, and the first gate insulating film and the second gate insulating film are different from each other in nitrogen concentration profile.
摘要翻译：半导体器件包括N型MOS晶体管和P型MOS晶体管。 N型MOS晶体管具有第一栅极绝缘膜和第一栅极电极。 P型MOS晶体管具有第二栅极绝缘膜和第二栅极电极。第一栅极绝缘膜和第二栅极绝缘膜由氮氧化硅制成，并且第一栅极绝缘膜和第二栅极绝缘膜在氮浓度分布中彼此不同。

23. 发明申请

US20080036008A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080036008A1
公开(公告)日：2008-02-14
申请号：US11882499
申请日：2007-08-02
申请人： Junji Hirase , Yoshihiro Sato
发明人： Junji Hirase , Yoshihiro Sato
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L21/823878
摘要： A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes: a first gate insulating film formed on a first active region of a substrate; and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes: a second gate insulating film formed on a second active region of the substrate and having a dielectric constant lower than the first gate insulating film; and a second gate electrode formed on the second gate insulating film. Insulting sidewall spacers having the same structure are formed on respective side faces of the first gate electrode and the second gate electrode.
摘要翻译：半导体器件包括第一MIS晶体管和第二MIS晶体管。第一MIS晶体管包括：形成在基板的第一有源区上的第一栅极绝缘膜; 以及形成在第一栅极绝缘膜上的第一栅电极。第二MIS晶体管包括：形成在基板的第二有源区上并具有低于第一栅极绝缘膜的介电常数的第二栅极绝缘膜; 以及形成在第二栅极绝缘膜上的第二栅电极。在第一栅电极和第二栅电极的相应侧面上形成具有相同结构的绝缘侧壁间隔物。

24. 发明授权

US5362982A Insulated gate FET with a particular LDD structure 失效
标题翻译：具有特定LDD结构的绝缘栅FET
公开(公告)号：US5362982A
公开(公告)日：1994-11-08
申请号：US040196
申请日：1993-04-01
申请人： Junji Hirase , Takashi Hori
发明人： Junji Hirase , Takashi Hori
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/7836
摘要： A lightly doped source and a lightly doped drain are formed at a region which is adjacent to a heavily doped source and a heavily doped drain of FET and all or a part of which is under a gate electrode. In the lightly doped source and the lightly doped drain, an effective impurity atom concentration is gradually lowered from an inside of a substrate toward a surface thereof. Accordingly, a capacity between the gate and the drain is reduced and an operation speed of a circuit is enhanced. Hot carrier is generated at a deeper portion, which leads to an improvement for hot-carrier immunity. In a method of manufacturing it, only by changing conditions of implant and heat-treatment at manufacturing an FET with a conventional LATID structure the impurity atom concentration profile is improved. The effective impurity atom concentration at surfaces of lightly doped source and drain can be lowered by counter-doping.
摘要翻译：在与重掺杂源和FET的重掺杂漏极相邻的区域处形成轻掺杂源和轻掺杂漏极，其全部或一部分位于栅电极下。在轻掺杂源和轻掺杂漏极中，有效的杂质原子浓度从衬底的内部朝向其表面逐渐降低。因此，栅极和漏极之间的容量减小，并且电路的操作速度提高。在更深的部分产生热载体，这导致热载体免疫性的改善。在其制造方法中，只有通过改变具有常规LATID结构的FET制造时的注入和热处理条件，才能提高杂质原子浓度分布。通过反掺杂可以降低轻掺杂源极和漏极表面的有效杂质原子浓度。

25. 发明申请

US20070069312A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070069312A1
公开(公告)日：2007-03-29
申请号：US11491266
申请日：2006-07-24
申请人： Yoshihiro Satou , Junji Hirase
发明人： Yoshihiro Satou , Junji Hirase
IPC分类号： H01L29/94
CPC分类号： H01L21/823475 , H01L21/28097 , H01L21/28114 , H01L21/28518 , H01L21/823443 , H01L23/485 , H01L29/42376 , H01L29/4975 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and surrounded by the isolation region; a fully-silicided gate line formed on the isolation region and the active region; and an insulating sidewall continuously covering a side face of the gate line. At least a portion of the gate line has a projection projecting from the sidewall.
摘要翻译：半导体器件包括：形成在半导体衬底中的隔离区; 形成在半导体衬底中并被隔离区包围的有源区; 形成在所述隔离区域和所述有源区域上的全硅化栅极线; 以及连续地覆盖栅极线的侧面的绝缘侧壁。栅极线的至少一部分具有从侧壁突出的突起。

26. 发明授权

US07037733B2 Method for measuring temperature, annealing method and method for fabricating semiconductor device 有权
标题翻译：测量温度的方法，退火方法和制造半导体器件的方法
公开(公告)号：US07037733B2
公开(公告)日：2006-05-02
申请号：US10343762
申请日：2002-07-01
申请人： Satoshi Shibata , Junji Hirase , Tatsuo Sugiyama , Emi Kanasaki , Fumitoshi Kawase , Yasushi Naito
发明人： Satoshi Shibata , Junji Hirase , Tatsuo Sugiyama , Emi Kanasaki , Fumitoshi Kawase , Yasushi Naito
IPC分类号： H01L21/66 , G01N25/00 , G01J5/00
CPC分类号： G01J5/0003
摘要： When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ε, such as a DPS film, is formed on the reverse face of the substrate 10.
摘要翻译：当在衬底10的退火处理期间测量衬底10的反面上的发射率ε时，由用于形成插头15A的第一DPS膜15，例如用于形成插头15A的第一DPS膜15的材料制成的膜，第二用于形成用于形成电容器上电极20A的电容器下电极17A和第三DPS膜20的DPS膜17形成在基板10的顶面上。另一方面，没有由材料制成的膜在基板10的背面上形成改变发射率ε（例如DPS膜）。

27. 发明授权

US5641699A Method of manufacturing a semiconductor device having a dummy cell 失效
标题翻译：制造具有虚设电池的半导体器件的方法
公开(公告)号：US5641699A
公开(公告)日：1997-06-24
申请号：US502557
申请日：1995-07-14
申请人： Junji Hirase , Shin Hashimoto
发明人： Junji Hirase , Shin Hashimoto
IPC分类号： H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/108 , H01L27/105
摘要： In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.
摘要翻译：在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。在集成电路区域中，设置多个单元形成区，分别由隔离限定。每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。所有虚拟细胞可能是缺乏伪细胞的P-N。因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

28. 发明授权

US08129794B2 Semiconductor device including MISFETs having different threshold voltages 有权
标题翻译：包括具有不同阈值电压的MISFET的半导体器件
公开(公告)号：US08129794B2
公开(公告)日：2012-03-06
申请号：US12357869
申请日：2009-01-22
申请人： Junji Hirase
发明人： Junji Hirase
IPC分类号： H01L21/336
CPC分类号： H01L21/82345 , H01L21/26513 , H01L29/105 , H01L29/517 , Y10S257/901
摘要： A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion.
摘要翻译：半导体器件包括第一MIS晶体管和具有高于第一MIS晶体管的阈值电压的阈值电压的第二MIS晶体管。第一MIS晶体管包括由形成在第一沟道区上的高k绝缘膜制成的第一栅极绝缘膜和具有设置在第一栅极绝缘膜上并与第一栅极绝缘膜接触的第一导电部分的第一栅电极和第二导电部分。第二MIS晶体管包括由形成在第二沟道区上的高k绝缘膜制成的第二栅极绝缘膜和具有设置在第二栅极绝缘膜上并与第二栅极绝缘膜接触的第三导电部分的第二栅电极和第四导电部分。第三导电部分的膜厚度小于第一导电部分的厚度，并且由与第一导电部分相同的组成材料制成。

29. 发明授权

US07804146B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07804146B2
公开(公告)日：2010-09-28
申请号：US12028392
申请日：2008-02-08
申请人： Hiroshi Ohkawa , Junji Hirase , Hisashi Ogawa , Kenji Yoneda
发明人： Hiroshi Ohkawa , Junji Hirase , Hisashi Ogawa , Kenji Yoneda
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L27/092 , H01L27/0922 , H01L29/518
摘要： A semiconductor device includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor has a first gate insulating film and a first gate electrode. The P-type MOS transistor has a second gate insulating film and a second gate electrode. The first gate insulating film and the second gate insulating film are made of silicon oxynitride, and the first gate insulating film and the second gate insulating film are different from each other in nitrogen concentration profile.
摘要翻译：半导体器件包括N型MOS晶体管和P型MOS晶体管。 N型MOS晶体管具有第一栅极绝缘膜和第一栅极电极。 P型MOS晶体管具有第二栅极绝缘膜和第二栅极电极。第一栅极绝缘膜和第二栅极绝缘膜由氮氧化硅制成，并且第一栅极绝缘膜和第二栅极绝缘膜在氮浓度分布中彼此不同。

30. 发明申请

US20070018251A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070018251A1
公开(公告)日：2007-01-25
申请号：US11489539
申请日：2006-07-20
申请人： Junji Hirase , Atsuhiro Kajiya
发明人： Junji Hirase , Atsuhiro Kajiya
IPC分类号： H01L29/94
CPC分类号： H01L21/823412 , H01L21/32155 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7845
摘要： In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region with the part of the gate electrode.
摘要翻译：在MIEET中，改变晶格常数的杂质被引入到位于隔离区上的栅电极的一部分中。在栅电极的一部分中产生的作为起点并且提高载流子迁移率的应力施加到与栅电极的一部分的沟道区。

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