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21. 发明申请

US20070241443A1 Isolating electric paths in semiconductor device packages 有权
标题翻译：隔离半导体器件封装中的电路径
公开(公告)号：US20070241443A1
公开(公告)日：2007-10-18
申请号：US11403626
申请日：2006-04-13
申请人： Adrian Ong , Dong Jeong
发明人： Adrian Ong , Dong Jeong
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L21/485 , H01L23/5382 , H01L2924/0002 , H01L2924/00
摘要： Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.
摘要翻译：用于减少半导体器件封装中的功率消耗或信号失真的方法，系统和装置。半导体器件封装包括第一电路中的半导体器件，第一电路，第二电路和隔离元件。第二电路与第一电路电连接，该装置的功能单元。隔离元件将第一电路中的隔离部分与第二电路分离，其中隔离元件被配置为当信号通过第二电通路时减小隔离部分中的电流。

22. 发明申请

US20070113126A1 Testing and Recovery in a Multilayer Device 有权
标题翻译：多层设备中的测试和恢复
公开(公告)号：US20070113126A1
公开(公告)日：2007-05-17
申请号：US11538799
申请日：2006-10-04
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/72
摘要： Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.
摘要翻译：公开了制造电子器件的系统和方法，其包括安装在晶片级的另一个下层电路上的辅助电路。辅助电路通过微尺度互连电连接到底层电路。该系统能够使用底层电路内的接口来测试辅助电路和/或互连。例如，可以对辅助电路进行测试，尽管它被安装成使得互连是隐藏的，即在使用常规测试系统和方法组装之后不能进行测试。这些系统和方法还允许包括可以被重新配置的多余电路和/或多余的互连以替代在测试期间发现有缺陷的辅助电路和/或微尺度互连的部分。

23. 发明申请

US20070094555A1 Component testing and recovery 有权
标题翻译：组件测试和恢复
公开(公告)号：US20070094555A1
公开(公告)日：2007-04-26
申请号：US11258484
申请日：2005-10-24
申请人： Adrian Ong , Richard Egan
发明人： Adrian Ong , Richard Egan
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C29/56 , G11C29/76 , G11C29/81 , G11C2229/743 , G11C2229/763
摘要： Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be defective. The replacement process occurs after the excess circuits and defective circuits are included in an electronic device including the different device components. Identification of the defective circuits may occur before or after the defective circuits are incorporated in the electronic device. In some embodiments, systems and methods of the invention result in improved manufacturing yields as compared with the prior art.
摘要翻译：公开了制造电子设备的系统和方法。这些电子设备包括用作电子设备中发现有缺陷的电路的替代物的多余电路。多余电路被包含在与发现有缺陷的电路不同的器件部件中。替换处理发生在多余电路和故障电路包括在包括不同器件组件的电子设备中之后。有缺陷的电路的识别可能发生在电路装置内的故障电路之前或之后。在一些实施例中，与现有技术相比，本发明的系统和方法导致改进的制造产量。

24. 发明申请

US20060279308A1 Electronic device having an interface supported testing mode 有权
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：US20060279308A1
公开(公告)日：2006-12-14
申请号：US11207665
申请日：2005-08-18
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路芯片相关联的第一集成电路芯片的系统，其中半导体器件的至少一些外部端子将由第一和第二集成电路芯片共享，并且其中第一个集成电路芯片设计用于正常操作和测试模式。该系统包括多个多路复用器电路。当第一集成电路芯片处于正常操作时，每个复用器电路可操作以从第二集成电路芯片接收相应的信号。当第一集成电路芯片处于测试模式时，每个复用器电路还可操作以从第二集成电路芯片或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路芯片在正常操作和测试模式之间转变的信号

25. 发明申请

US20060253266A1 Integrated circuit test array including test module 有权
标题翻译：集成电路测试阵列包括测试模块
公开(公告)号：US20060253266A1
公开(公告)日：2006-11-09
申请号：US11479061
申请日：2006-06-30
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G06F19/00
CPC分类号： G01R31/31922 , G11C29/1201 , G11C29/48 , G11C29/56 , G11C29/56004 , G11C29/56012 , G11C2029/5602 , G11C2029/5606 , G11C2207/104
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
摘要翻译：公开了测试集成电路的系统和方法。该系统包括被配置为在自动测试设备和要测试的集成电路之间操作的测试模块。测试接口被配置为以比自动化测试设备配置为运行的更高的时钟频率测试集成电路。为了这样做，测试接口包括被配置用于生成要提供给集成电路的地址和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。

26. 发明申请

US20060152241A1 Shared bond pad for testing a memory within a packaged semiconductor device 有权
标题翻译：用于测试封装的半导体器件内的存储器的共用焊盘
公开(公告)号：US20060152241A1
公开(公告)日：2006-07-13
申请号：US11223286
申请日：2005-09-09
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/31723 , G01R31/31701 , G01R31/3172 , G01R31/318513 , G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/3602 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.
摘要翻译：提供了一种用于通过其共享的外部端子与封装的半导体器件内的器件通信的系统。作为一个示例，系统提供测试包内的存储器。除了设备和共享外部终端之外，系统还包括一个接收多个命令信号的命令寄存器，以及耦合在外部终端和命令寄存器之间的数字逻辑器件。每个数字逻辑器件接收不同的时钟信号，并将命令信号之一输出到命令寄存器。以与时钟信号协调的顺序将命令信号提供给外部终端，使得每个数字逻辑设备缓冲命令信号之一。

27. 发明授权

US08907639B2 Boost power converter with high-side active damping in discontinuous conduction mode 有权
标题翻译：在不连续导通模式下具有高侧有源阻尼的升压功率转换器
公开(公告)号：US08907639B2
公开(公告)日：2014-12-09
申请号：US13193311
申请日：2011-07-28
申请人： Rendon Holloway , Adrian Ong , Howard Hou
发明人： Rendon Holloway , Adrian Ong , Howard Hou
IPC分类号： G05F1/00 , H02M3/158
CPC分类号： H02M3/158 , H02J1/02
摘要： A boost power converter system according to one embodiment includes an input voltage high-side node; an inductor coupled to the input voltage high-side node at a first terminal of the inductor; a power switch coupled to the inductor at a second terminal of the inductor; a drive circuit configured to control the power switch such that the boost power converter system operates in a discontinuous conduction mode when a load current drops below a critical conduction threshold; and a damping switch configured to enable current flow from the power switch at the second terminal of the inductor to the input voltage high-side node, wherein the damping switch is closed when the power switch is open and the damping switch is opened when the power switch is closed.
摘要翻译：根据一个实施例的升压功率转换器系统包括输入电压高侧节点; 电感器，其耦合到电感器的第一端处的输入电压高侧节点; 在所述电感器的第二端子处耦合到所述电感器的功率开关; 驱动电路，被配置为控制所述功率开关，使得当负载电流下降到临界导通阈值以下时，所述升压功率转换器系统工作在不连续导通模式; 以及阻尼开关，其构造成使得能够从电感器的第二端子处的电力开关到输入电压高侧节点的电流流动，其中当电源开关断开时阻尼开关闭合，并且阻尼开关在电力开关关闭。

28. 发明申请

US20080089139A1 Memory accessing circuit system 有权
标题翻译：存储器存取电路系统
公开(公告)号：US20080089139A1
公开(公告)日：2008-04-17
申请号：US11906731
申请日：2007-10-02
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/10 , G11C8/10 , G11C8/12 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/04 , G11C29/50012 , G11C2029/0401 , G11C2029/5602
摘要： A configurable memory system and method is described wherein an integrated circuit coupled to a memory device includes application logic and memory interface logic in communication with the application logic, the memory interface logic configured to access a memory array within the memory device. The memory interface logic provides logic functions and/or signals that would have been provided by logic on a prior art memory device. The interface logic may access the memory device synchronously or asynchronously. The integrated circuit may communicate to the memory device using multiplexed or non-multiplexed signals.
摘要翻译：描述了可配置的存储器系统和方法，其中耦合到存储器件的集成电路包括与应用逻辑通信的应用逻辑和存储器接口逻辑，存储器接口逻辑被配置为访问存储器设备内的存储器阵列。存储器接口逻辑提供逻辑功能和/或由现有技术存储器件上的逻辑提供的信号。接口逻辑可以同步或异步地访问存储设备。集成电路可以使用复用或非复用信号与存储器件进行通信。

29. 发明申请

US20080063126A1 Delay Lock Loop Delay Adjusting Method and Apparatus 有权
标题翻译：延迟锁定环路延迟调整方法和装置
公开(公告)号：US20080063126A1
公开(公告)日：2008-03-13
申请号：US11853006
申请日：2007-09-10
申请人： Adrian Ong , Douglas Gorgen
发明人： Adrian Ong , Douglas Gorgen
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/0818
摘要： Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.
摘要翻译：用于同步设备之间通信的系统和方法包括使用测试电路来测量通过延迟电路的传播时间。传播时间用于确定延迟锁定循环内的初始延迟值。然后改变该延迟值，直到找到导致同步的优选延迟值。在各种实施例中，使用初始延迟值增加了同步的速度，可靠性或其它有益特征。

30. 发明申请

US20070168808A1 Integrated circuit testing module including data compression 有权
标题翻译：集成电路测试模块包括数据压缩
公开(公告)号：US20070168808A1
公开(公告)日：2007-07-19
申请号：US11369878
申请日：2006-03-06
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/28
CPC分类号： G01R31/31922 , G01R31/31905 , G01R31/31926 , G01R31/31928 , G06F11/263 , G11C29/14 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
摘要翻译：公开了测试集成电路的系统和方法。这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。测试接口被配置为以比自动化测试设备配置为运行的更高的时钟频率测试集成电路。为了这样做，测试接口包括被配置用于生成要提供给集成电路的地址和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。

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