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21. 发明授权

US11887529B2 Pixel array 有权
公开(公告)号：US11887529B2
公开(公告)日：2024-01-30
申请号：US17723472
申请日：2022-04-19
申请人： Au Optronics Corporation
发明人： Ya-Jung Wang , Jing-Wun Jhang , Rong-Fu Lin , Nien-Chen Li , Hsien-Chun Wang , Che-Chia Chang , June Woo Lee , Hsin-Ying Lin , Chia-Ting Hsieh , Chien-Fu Huang , Sung-Yu Su
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2330/021
摘要： A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

22. 发明申请

US20220335886A1 PIXEL ARRAY 有权
公开(公告)号：US20220335886A1
公开(公告)日：2022-10-20
申请号：US17723472
申请日：2022-04-19
申请人： Au Optronics Corporation
发明人： Ya-Jung Wang , Jing-Wun Jhang , Rong-Fu Lin , Nien-Chen Li , Hsien-Chun Wang , Che-Chia Chang , June Woo Lee , Hsin-Ying Lin , Chia-Ting Hsieh , Chien-Fu Huang , Sung-Yu Su
IPC分类号： G09G3/32
摘要： A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

23. 发明授权

US11355045B2 Display device and multiplexer circuit thereof 有权
公开(公告)号：US11355045B2
公开(公告)日：2022-06-07
申请号：US17201138
申请日：2021-03-15
申请人： AU Optronics Corporation
发明人： Rong-Fu Lin , Chi Yu , Chih-Fu Yang , Jie-Chuan Huang , Sung-Yu Su
IPC分类号： G09G3/20
摘要： A multiplexer circuit includes a first switch unit and a second switch unit. The first switch unit is electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration. The second switch unit is electrically connected to the first data line and a second pixel circuit, and configured to turn on according to a second signal in a second time duration. The first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap.

24. 发明授权

US11264413B2 Display device having common electrode overlapping capacitor electrode and pixel electrode 有权
公开(公告)号：US11264413B2
公开(公告)日：2022-03-01
申请号：US16535067
申请日：2019-08-08
申请人： Au Optronics Corporation
发明人： Yu-Min Chi , Sung-Yu Su , Pin-Miao Liu
IPC分类号： H01L27/12 , G02F1/1335 , G02F1/1362 , G02F1/1368
摘要： A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main-driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main-driving element includes a first main-gate, a first main-channel layer, a first main-source, and a first main-drain. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first capacitor electrode is electrically connected with the first main-drain and the first sub-source. The first pixel electrode is electrically connected with the first sub-drain. The common electrode and the first capacitor electrode have a first main capacitor therebetween. The common electrode and the first pixel electrode have a first sub capacitor therebetween.

25. 发明授权

US11011105B2 Pixel circuit 有权
公开(公告)号：US11011105B2
公开(公告)日：2021-05-18
申请号：US16828928
申请日：2020-03-24
申请人： Au Optronics Corporation
发明人： Hsien-Chun Wang , Ya-Jung Wang , Jing-Wun Jhang , Chen-Feng Fan , Wan-Heng Chang , Sung-Yu Su
IPC分类号： G09G3/32
摘要： A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

26. 发明申请

US20210104192A1 PIXEL ARRAY SUBSTRATE 有权
公开(公告)号：US20210104192A1
公开(公告)日：2021-04-08
申请号：US16871066
申请日：2020-05-11
申请人： Au Optronics Corporation
发明人： Shu-Hao Huang , Sung-Yu Su
IPC分类号： G09G3/20
摘要： A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first multiplexer, a second multiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first multiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second multiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first multiplexer. The second connecting line is electrically connected to the second multiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.

27. 发明授权

US10971093B2 Pixel circuit and display device 有权
公开(公告)号：US10971093B2
公开(公告)日：2021-04-06
申请号：US16239686
申请日：2019-01-04
申请人： AU OPTRONICS CORPORATION
发明人： Peng-Bo Xi , Sung-Yu Su , Chen-Feng Fan , Wan-Heng Chang
IPC分类号： G09G3/36
摘要： A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor.

28. 发明授权

US10916181B2 Display device 有权
公开(公告)号：US10916181B2
公开(公告)日：2021-02-09
申请号：US16700855
申请日：2019-12-02
申请人： AU Optronics Corporation
发明人： Rong-Fu Lin , Kai-Wei Hong , Jie-Chuan Huang , Peng-Bo Xi , Sung-Yu Su
IPC分类号： G06F3/038 , G09G5/00 , G09G3/20 , G06F3/041
摘要： A display device comprising an active area and a surrounding area is provided. The active area includes a common electrode for receiving a common voltage. The surrounding area is located at a side of the active area, and the surrounding area includes a shielding metal layer and a surrounding circuit. The shielding metal layer is electrically isolated from the common electrode and receives a shielding voltage. The surrounding circuit and a first shielding metal are overlapped in a vertical projection direction, and the common voltage is power-isolated from the shielding voltage.

29. 发明申请

US20200185432A1 ARRAY SUBSTRATE AND METHOD FOR FABRICATING THEREOF 审中-公开
公开(公告)号：US20200185432A1
公开(公告)日：2020-06-11
申请号：US16792291
申请日：2020-02-16
申请人： Au Optronics Corporation
发明人： Shu-Hao Huang , Chin-Chuan Liu , Sung-Yu Su
IPC分类号： H01L27/12 , H01L29/786 , G02F1/1368 , G02F1/1362 , G02F1/1333
摘要： A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

30. 发明授权

US10615195B2 Array substrate with openings in insulation layer for auxiliary elecrode 有权
公开(公告)号：US10615195B2
公开(公告)日：2020-04-07
申请号：US15784211
申请日：2017-10-16
申请人： Au Optronics Corporation
发明人： Shu-Hao Huang , Chin-Chuan Liu , Sung-Yu Su
IPC分类号： H01L27/12 , G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L29/786
CPC分类号： H01L27/1288 , G02F1/1368 , G02F1/133345 , G02F1/136227 , H01L27/124 , H01L27/127 , H01L27/1222 , H01L27/1244 , H01L27/1248 , H01L27/1259 , H01L29/78621 , H01L29/78633 , H01L29/78675 , G02F2001/136231 , G02F2201/123 , G02F2202/104
摘要： A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

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