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21. 发明授权

US10409738B2 Information switching 有权
公开(公告)号：US10409738B2
公开(公告)日：2019-09-10
申请号：US15742164
申请日：2016-08-23
申请人： ARM LIMITED
发明人： Syed Ali Raza Jafri , Stephan Diestelhorst
IPC分类号： G06F13/00 , G06F13/16 , H04L12/40 , H04L12/801 , H04L12/937 , H04L12/935 , G06F13/40 , H04L12/933
摘要： An information switch comprises a plurality of input circuits and a plurality of output circuits, the information switch being configured to communicate information units between the input circuits and the output circuits in successive transmission cycles; each input circuit being configured, in dependence upon a queue of one or more information units for transmission via that input circuit and in dependence upon hint data received in respect of a current transmission cycle, to send an information unit transmission request to one or more of the output circuits; and each output circuit being configured, in response to one or more information unit transmission requests received from respective input circuits, to select an input circuit for information unit transmission to that output circuit in a current transmission cycle and to provide hint data indicating a provisional selection, by that output circuit, of an input circuit at a next transmission cycle.

22. 发明授权

US09946492B2 Controlling persistent writes to non-volatile memory based on persist buffer data and a persist barrier within a sequence of program instructions 有权
公开(公告)号：US09946492B2
公开(公告)日：2018-04-17
申请号：US14927725
申请日：2015-10-30
申请人： ARM Limited , The Regents of the University of Michigan
发明人： Stephan Diestelhorst , Aasheesh Kolli , Ali Ghassan Saidi , Peter Chen , Thomas Friedrich Wenisch
IPC分类号： G06F12/00 , G06F13/00 , G06F3/06 , G11C16/10 , G06F13/28 , G06F12/02
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0629 , G06F3/0679 , G06F12/0246 , G06F13/00 , G11C16/102
摘要： A data processing system 2 including non-volatile memory 22 manages the ordering of writes to the non-volatile memory and persist barrier instructions using a persist buffer storing persist buffer data. A write controller responds to the persist buffer data to prevent writing to the non-volatile memory for instructions following a given persist barrier instruction within a sequence of program instructions before the writes to the non-volatile memory which precede that given persist barrier instruction have at least been acknowledged as received by the memory system containing the non-volatile memory. In the case of a multi-core system, cache snooping mechanisms are used to pass persistency dependence data between cores such that strong persist atomicity may be tracked and managed between the cores.

23. 发明授权

US10795815B2 Method and apparatus for maintaining data coherence in a non-uniform compute device 有权
公开(公告)号：US10795815B2
公开(公告)日：2020-10-06
申请号：US15166458
申请日：2016-05-27
申请人： ARM Limited
发明人： Jonathan Curtis Beard , Wendy Elsasser , Stephan Diestelhorst
IPC分类号： G06F12/0815 , G06F12/0811 , G06F12/084 , G06F12/08 , G06F15/78 , G06F9/38
摘要： A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

24. 发明授权

US10761988B2 Methods and apparatus of cache access to a data array with locality-dependent latency characteristics 有权
公开(公告)号：US10761988B2
公开(公告)日：2020-09-01
申请号：US16142330
申请日：2018-09-26
申请人： Arm Limited
发明人： Radhika Sanjeev Jagtap , Nikos Nikoleris , Andreas Lars Sandberg , Stephan Diestelhorst
IPC分类号： G06F12/0864 , G06F12/1045
摘要： Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.

25. 发明授权

US10635325B2 Managing persistent storage writes in electronic systems 有权
公开(公告)号：US10635325B2
公开(公告)日：2020-04-28
申请号：US15358885
申请日：2016-11-22
申请人： ARM Limited
发明人： Kshitij Sudan , Stephan Diestelhorst , Michael Andrew Campbell
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0659 , G06F3/0679
摘要： The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.

26. 发明授权

US10628318B2 Cache sector usage prediction 有权
公开(公告)号：US10628318B2
公开(公告)日：2020-04-21
申请号：US15882104
申请日：2018-01-29
申请人： ARM Limited
发明人： Nikos Nikoleris , Andreas Lars Sandberg , Jonas S̆vedas , Stephan Diestelhorst
IPC分类号： G06F12/0871 , G06F12/084 , G06F3/06 , G06F12/0862 , G06F12/0895 , G06F12/0808 , G06F12/0811
CPC分类号： G06F12/0871 , G06F3/064 , G06F12/084 , G06F12/0808 , G06F12/0811 , G06F12/0862 , G06F12/0895 , G06F2212/6026
摘要： A system cache and method of operating a system cache are provided. The system cache provides data caching in response to data access requests from plural system components. The system cache has data caching storage with plural entries, each entry storing a block of data items and each block of data items comprising plural sectors of data items. Sector use prediction circuitry is provided which stores a set of sector use pattern entries. In response to a data access request received from a system component specifying one or more data items, a pattern entry is selected and a sector use prediction is generated in dependence on a sector use pattern in the selected pattern entry. Further data items may then be retrieved which are not specified in the data access request but are indicated by the sector use prediction.

27. 发明申请

US20200050541A1 APPARATUS AND METHODS TO PROLONG LIFETIME OF MEMORIES 审中-公开
公开(公告)号：US20200050541A1
公开(公告)日：2020-02-13
申请号：US16478544
申请日：2018-01-09
申请人： Arm Limited
发明人： Ireneus Johannes de Jong , Andres Amaya Garcia , Stephan Diestelhorst
IPC分类号： G06F12/02 , G06F12/0868 , G06F12/0873 , G06F11/07 , G11C11/409
摘要： Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

28. 发明授权

US10552152B2 Method and apparatus for scheduling in a non-uniform compute device 有权
公开(公告)号：US10552152B2
公开(公告)日：2020-02-04
申请号：US15166444
申请日：2016-05-27
申请人： ARM Limited
发明人： Jonathan Curtis Beard , Wendy Elsasser , Eric Van Hensbergen , Stephan Diestelhorst
IPC分类号： G06F9/30 , G06F12/084 , G06F12/0811 , G06F9/38 , G06F12/0875 , G06F12/0897
摘要： A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

29. 发明申请

US20190004960A1 APPARATUS AND METHOD OF HANDLING CACHING OF PERSISTENT DATA 审中-公开
公开(公告)号：US20190004960A1
公开(公告)日：2019-01-03
申请号：US16005934
申请日：2018-06-12
申请人： ARM Limited
发明人： Wei Wang , Stephan Diestelhorst , Wendy Arnott ELSASSER , Andreas Lars Sandberg , Nikos NIKOLERIS
IPC分类号： G06F12/0873 , G06F12/0871 , G06F12/02 , G06F12/0895 , G06F1/32
摘要： An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.

30. 发明授权

US10133675B2 Data processing apparatus, and a method of handling address translation within a data processing apparatus 有权
公开(公告)号：US10133675B2
公开(公告)日：2018-11-20
申请号：US15325250
申请日：2015-06-22
申请人： ARM LIMITED
发明人： Andreas Hansson , Ali Saidi , Aniruddha Nagendran Udipi , Stephan Diestelhorst
IPC分类号： G06F12/10 , G06F12/1036 , G06F12/0862 , G06F12/1009 , G06F12/1027
摘要： A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

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