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21. 发明申请

US20120173850A1 INFORMATION PROCESSING APPARATUS 有权
标题翻译：信息处理装置
公开(公告)号：US20120173850A1
公开(公告)日：2012-07-05
申请号：US13423145
申请日：2012-03-16
申请人： Teppei HIROTSU , Yuuichi ABE , Takeshi KATAOKA , Yasuhiro NAKATSUKA
发明人： Teppei HIROTSU , Yuuichi ABE , Takeshi KATAOKA , Yasuhiro NAKATSUKA
IPC分类号： G06F9/38 , G06F13/40 , G06F9/312
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/382
摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
摘要翻译：能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

22. 发明授权

US08095825B2 Error correction method with instruction level rollback 有权
标题翻译：具有指令级回滚的纠错方法
公开(公告)号：US08095825B2
公开(公告)日：2012-01-10
申请号：US11623441
申请日：2007-01-16
申请人： Teppei Hirotsu , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei Hirotsu , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，寄存器文件的内容由延迟的寄存器文件恢复，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

23. 发明申请

US20110049988A1 Control System and Semiconductor Device Used Therein 审中-公开
标题翻译：其中使用的控制系统和半导体装置
公开(公告)号：US20110049988A1
公开(公告)日：2011-03-03
申请号：US12855428
申请日：2010-08-12
申请人： Nobuyasu KANEKAWA , Teppei HIROTSU , Itaru TANABE , Shuichi MIYAOKA , Ryoichi OURA
发明人： Nobuyasu KANEKAWA , Teppei HIROTSU , Itaru TANABE , Shuichi MIYAOKA , Ryoichi OURA
IPC分类号： H02J4/00
CPC分类号： G05F1/46 , B60L2240/441 , B60L2240/445 , B60L2240/486 , B60W2510/0638 , B60W2510/0676 , B60W2540/10 , B60W2540/16 , Y10T307/445
摘要： The present invention aims to provide a control system which is capable of building high-precision current detecting means in a single-chip LSI and can be realized at a lower cost, and a semiconductor device used in the control system. Drive circuits are provided inside the same semiconductor chip. The drive circuits are equipped with: current detecting shunt resistors each of which is provided in each of the drive circuits and detects a current flowing through a load, the current detecting shunt resistors being provided within a semiconductor chip by the same process; a dummy resistor provided within the semiconductor chip by the same process as the current detecting shunt resistors; and a calibration reference externally attached to the semiconductor chip and connected to the dummy resistor. A correcting means corrects the values of currents that flow through the current detecting shunt resistors, using the dummy resistor and the calibration reference.
摘要翻译：本发明旨在提供一种能够在单芯片LSI中构建高精度电流检测装置并且可以以较低成本实现的控制系统以及在控制系统中使用的半导体装置。驱动电路设置在同一半导体芯片的内部。驱动电路配备有电流检测分流电阻器，每个驱动电路设置在每个驱动电路中并检测流过负载的电流，电流检测分流电阻器通过相同的工艺设置在半导体芯片内; 通过与电流检测分流电阻器相同的工艺在半导体芯片内提供虚拟电阻器; 以及外部附接到半导体芯片并连接到虚拟电阻器的校准参考。校正装置使用虚拟电阻器和校准基准校正流过电流检测分流电阻器的电流值。

24. 发明申请

US20080077745A1 Data processing device 审中-公开
标题翻译：数据处理装置
公开(公告)号：US20080077745A1
公开(公告)日：2008-03-27
申请号：US11890902
申请日：2007-08-07
申请人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
发明人： Teppei Hirotsu , Kotaro Shimamura , Yasuo Watanabe
IPC分类号： G06F12/02
CPC分类号： G06F12/0802 , G06F12/08 , G06F2212/401
摘要： A data processing device that does not depend on the type of data, has wide application range, and can reduce memory access in data transfer via a buffer arranged in a memory is provided. In a data processing device including a plurality of data processing units and a memory commonly accessed by the data processing units, the data processing units transfer the transfer data via the memory, the transfer data and the compressed data of the transfer data are held in the memory. When read request for the data is issued, the compressed data is expanded and the expanded data is stored in the expanding data buffer. While the compressed data is being expanded, the original data is read from the memory, and after the expanded data is stored in the expanding data buffer, the expanded data is read from the expanding data buffer.
摘要翻译：提供了不依赖于数据类型的数据处理设备，具有广泛的应用范围，并且可以经由布置在存储器中的缓冲器的数据传输中减少存储器访问。在包括多个数据处理单元和由数据处理单元共同访问的存储器的数据处理设备中，数据处理单元经由存储器传送传送数据，传送数据和传送数据的压缩数据保存在记忆。当发出对数据的读取请求时，压缩数据被扩展，扩展数据被存储在扩展数据缓冲器中。当压缩数据被扩展时，从存储器读取原始数据，并且在扩展数据被存储在扩展数据缓冲器中之后，从扩展数据缓冲器中读出扩展数据。

25. 发明授权

US06609232B2 Logic compound method and logic compound apparatus 失效
标题翻译：逻辑复合法和逻辑复合器
公开(公告)号：US06609232B2
公开(公告)日：2003-08-19
申请号：US09791818
申请日：2001-02-26
申请人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
发明人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.
摘要翻译：在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

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