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21. 发明授权

US06691168B1 Method and apparatus for high-speed network rule processing 有权
标题翻译：用于高速网络规则处理的方法和装置
公开(公告)号：US06691168B1
公开(公告)日：2004-02-10
申请号：US09246572
申请日：1999-02-08
申请人： Subhash Bal , Raghunath Iyer , Sundar Iyer , Ramana Rao
发明人： Subhash Bal , Raghunath Iyer , Sundar Iyer , Ramana Rao
IPC分类号： G06F15173
CPC分类号： H04L63/0263 , H04L29/06 , H04L29/12009 , H04L49/205 , H04L49/25 , H04L49/50 , H04L61/00 , H04L63/0227 , H04L63/1416 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22
摘要： As Internet packet flow increases, the demand for high speed packet filtering has grown. The present invention introduces several methods for a high-speed rule processing. The methods are geared towards Internet Protocol (IP) packet processing.
摘要翻译：随着互联网分组流量的增加，对高速分组过滤的需求也在增长。本发明引入了用于高速规则处理的几种方法。这些方法面向互联网协议（IP）数据包处理。

22. 发明申请

US20150003148A1 Methods and Apparatus for Designing and Constructing Dual Write Memory Circuits with Voltage Assist 有权
标题翻译：用于设计和构造具有电压辅助的双写存储器电路的方法和装置
公开(公告)号：US20150003148A1
公开(公告)日：2015-01-01
申请号：US14274518
申请日：2014-05-09
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。因此，具有电压辅助的空间域复用允许单端写入来处理在单个周期中处理的两个独立的写操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

23. 发明申请

US20140185364A1 Methods And Apparatus For Designing And Constructing Multi-Port Memory Circuits 有权
标题翻译：用于设计和构造多端口存储器电路的方法和装置
公开(公告)号：US20140185364A1
公开(公告)日：2014-07-03
申请号：US13732372
申请日：2013-01-01
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C11/412
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.
摘要翻译：大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

24. 发明授权

US08677072B2 System and method for reduced latency caching 有权
标题翻译：降低延迟缓存的系统和方法
公开(公告)号：US08677072B2
公开(公告)日：2014-03-18
申请号：US12928698
申请日：2010-12-15
申请人： Sundar Iyer , Shang-Tse Chuang
发明人： Sundar Iyer , Shang-Tse Chuang
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0844 , G06F12/0851 , G06F12/0855 , G06F12/10
摘要： A reduced latency memory system that prevents memory bank conflicts. The reduced latency memory system receives a read request and write request. The read request is then handled by simultaneously fetching data from a main memory and a cache memory. The address of the read request is compared with a cache tag value and if the cache tag value matches the address of the read request, the data from the cache memory is served. The write request is stored and handled in a subsequent memory cycle.
摘要翻译：减少延迟的存储器系统，防止存储器冲突。减少延迟的存储器系统接收读请求和写请求。然后通过从主存储器和高速缓冲存储器同时提取数据来处理读请求。将读取请求的地址与缓存标签值进行比较，并且如果高速缓存标签值与读取请求的地址匹配，则来自高速缓冲存储器的数据被提供。写请求在随后的存储器周期中被存储和处理。

25. 发明申请

US20130258757A1 Methods And Apparatus For Synthesizing Multi-Port Memory Circuits 有权
标题翻译：用于合成多端口存储器电路的方法和装置
公开(公告)号：US20130258757A1
公开(公告)日：2013-10-03
申请号：US13434296
申请日：2012-03-29
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C8/16 , G11C11/00
CPC分类号： G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
摘要翻译：现代数字集成电路中通常需要多端口存储器电路来存储数据。多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

26. 发明申请

US20130046953A1 System And Method For Storing Data In A Virtualized High Speed Memory System With An Integrated Memory Mapping Table 有权
标题翻译：用于在具有集成存储器映射表的虚拟化高速存储器系统中存储数据的系统和方法
公开(公告)号：US20130046953A1
公开(公告)日：2013-02-21
申请号：US13570125
申请日：2012-08-08
申请人： Sundar Iyer , Shang-Tse Chuang
发明人： Sundar Iyer , Shang-Tse Chuang
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/06 , G06F12/0851 , G06F12/10 , G11C7/1075
摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.
摘要翻译：公开了一种用于提供高速存储器操作的系统和方法。该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。将虚拟内存地址映射到物理内存地址的可更改映射表存储在同一个内存系统中。

27. 发明申请

US20110145777A1 Intelligent memory system compiler 有权
标题翻译：智能内存系统编译器
公开(公告)号：US20110145777A1
公开(公告)日：2011-06-16
申请号：US12806946
申请日：2010-08-23
申请人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
发明人： Sundar Iyer , Sanjeev Joshi , Shang-Tse Chuang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0683 , G06F12/0844 , G06F12/0851 , G06F12/0855
摘要： Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.
摘要翻译：为集成电路设计存储器子系统可能是耗时且昂贵的任务。为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及存储器系统的测试套件。

28. 发明授权

US07136926B1 Method and apparatus for high-speed network rule processing 有权
标题翻译：用于高速网络规则处理的方法和装置
公开(公告)号：US07136926B1
公开(公告)日：2006-11-14
申请号：US09224382
申请日：1998-12-31
申请人： Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ramana Rao
发明人： Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ramana Rao
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L63/0263 , H04L29/06 , H04L29/12009 , H04L49/205 , H04L49/25 , H04L49/50 , H04L61/00 , H04L63/0227 , H04L63/1416 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22
摘要： As Internet packet flow increases, the demand for high speed packet filtering has grown. The present invention introduces a high-speed rule processing method that may be used for packet filtering. The method pre-processes a set of packet filtering rules such that the rules may be searched in parallel by a set of independent search units. Specifically, the rules are divided into N orthogonal dimensions that comprise aspects of each packet that may be examined and tested. Each of the N dimensions are then divided into a set of dimension rule ranges. Each rule range is assigned a value that specifies the rules that may apply in that range. The rule preprocessing is completed by creating a search structure to be used for classifying a packet into one of the rule ranges in each of the N dimensions. Each search structure may be used by an independent search unit such that all N dimensions may be searched concurrently. The packet processing method of the present invention activates the N independent search units to search the N pre-processor created search structures. The output of each of the N search structures is then logically combined to select a rule to be applied.
摘要翻译：随着互联网分组流量的增加，对高速分组过滤的需求也在增长。本发明引入了可用于包过滤的高速规则处理方法。该方法预处理一组包过滤规则，使得可以通过一组独立搜索单元并行搜索规则。具体地说，规则被划分成N个正交维度，其包括可以被检查和测试的每个分组的方面。然后将N个维度中的每一个分成一组维度规则范围。为每个规则范围分配一个值，该值指定可应用于该范围的规则。通过创建一个搜索结构来完成规则预处理，该搜索结构用于将数据包分类到每个N维中的规则范围之一。每个搜索结构可以由独立的搜索单元使用，使得可以同时搜索所有N个维度。本发明的分组处理方法激活N个独立搜索单元以搜索N个预处理器创建的搜索结构。然后将N个搜索结构中的每一个的输出逻辑地组合以选择要应用的规则。

29. 发明授权

US06611875B1 Control system for high speed rule processors 有权
标题翻译：高速规则处理器控制系统
公开(公告)号：US06611875B1
公开(公告)日：2003-08-26
申请号：US09305783
申请日：1999-04-30
申请人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
发明人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
IPC分类号： G06F1516
CPC分类号： H04L49/3009 , H04L29/06 , H04L29/12009 , H04L49/205 , H04L49/25 , H04L49/355 , H04L49/50 , H04L61/00 , H04L63/0227 , H04L63/0263 , H04L63/1416 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22
摘要： A control system for high-speed rule processors used in a gateway system is disclosed. The gateway system employing the current invention can process packets at wire speed by using massive parallel processors, each of the processors operating concurrently and independently. Further, the processing capacities in the gateway system employing the current invention are expandable. The number of packet inspector engines may be increased and all of the engines are connected in a cascade manner. Under the control system, all of the engines operate concurrently and independently and results from each of the engines are collected sequentially through a common data bus. As such the processing speed of packets becomes relatively independent of the complexities and numbers of rules that may be applied to the packets.
摘要翻译：公开了一种用于网关系统中的高速规则处理器的控制系统。采用本发明的网关系统可以通过使用大量的并行处理器以线速处理分组，每个处理器并行且独立地进行操作。此外，采用本发明的网关系统中的处理能力是可扩展的。可以增加分组检查器引擎的数量，并且所有引擎都以级联方式连接。在控制系统下，所有发动机同时并独立运行，每个发动机的结果通过公共数据总线顺序收集。因此，分组的处理速度变得相对独立于可应用于分组的规则的复杂性和数量。

30. 发明授权

US06510509B1 Method and apparatus for high-speed network rule processing 有权
标题翻译：用于高速网络规则处理的方法和装置
公开(公告)号：US06510509B1
公开(公告)日：2003-01-21
申请号：US09280235
申请日：1999-03-29
申请人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
发明人： Vikram Chopra , Ajay Desai , Raghunath Iyer , Sundar Iyer , Moti Jiandani , Ajit Shelat , Navneet Yadav
IPC分类号： G06F1500
CPC分类号： H04L69/16 , H04L29/06 , H04L49/90 , H04L69/12 , H04L69/161
摘要： A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.
摘要翻译：公开了一种高速规则处理装置，其可用于实现各种规则处理任务，例如网络地址转换，防火墙保护，服务质量，IP路由和/或负载平衡。高速规则处理器使用并行运行的比较引擎阵列。每个比较引擎包括用于存储指令和操作数的存储器，用于执行比较的算术逻辑和用于解释指令和操作数的控制电路。比较引擎阵列的结果优先使用优先级编码系统。

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