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21. 发明申请

US20120188114A1 MULTI-LAYERED ELECTROMAGNETIC WAVE ABSORBER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：多层电磁波吸收器及其制造方法
公开(公告)号：US20120188114A1
公开(公告)日：2012-07-26
申请号：US13314446
申请日：2011-12-08
申请人： Ki Yeon PARK , Seong Ho YOON , Eun Seok HONG
发明人： Ki Yeon PARK , Seong Ho YOON , Eun Seok HONG
IPC分类号： H01Q17/00 , B32B37/14 , B32B37/02
CPC分类号： H01Q17/00 , B32B38/08 , B32B2305/076 , B32B2307/204 , B32B2307/208 , B32B2315/085 , B32B2363/00 , B32B2457/00 , H05K9/0088
摘要： A multi layer electromagnetic wave absorber is provided. The absorber includes a surface layer comprising at least one of a dielectric lossy mixture and a magnetic lossy mixture, an absorption layer, laminated on a rear side of the surface layer, comprising: a dielectric lossy mixture having a higher loss than the dielectric lossy mixture for the surface layer, and a magnetic lossy mixture having a higher loss than the magnetic lossy mixture for the surface layer, and a boundary layer, laminated on a rear side of the absorption layer, comprising a conductive material.
摘要翻译：提供多层电磁波吸收体。吸收体包括表面层，该表面层包含介电损耗混合物和磁损耗混合物中的至少一种，层压在表面层后侧的吸收层，包括：具有比介电损耗混合物更高损耗的介电损耗混合物并且具有比用于表面层的磁损耗混合物损失高的磁损耗混合物和层叠在吸收层的后侧上的包含导电材料的边界层。

22. 发明申请

US20120113231A1 3D CAMERA 有权
标题翻译： 3D摄像机
公开(公告)号：US20120113231A1
公开(公告)日：2012-05-10
申请号：US13241599
申请日：2011-09-23
申请人： Il-do KIM , Byung-sun CHOI , Young-hoon JEONG , Hyun-seok HONG
发明人： Il-do KIM , Byung-sun CHOI , Young-hoon JEONG , Hyun-seok HONG
IPC分类号： H04N13/02
CPC分类号： H04N13/239 , H04N13/271 , H04N13/286
摘要： A three-dimensional (3D) camera and a method of operating the same are provided. The 3D camera includes: a first photographing lens unit; a first image sensor which obtains first image information of an object through the first photographing lens unit; a beam division unit disposed on an optical path between the first photographing lens unit and the first image sensor and which propagates light along a first path on which the first image sensor is positioned and along a second path that is different from the first path; a second photographing lens unit disposed on the second path; a second image sensor which obtains second image information of the object through the first photographing lens unit and the second photographing lens; and an image processing unit which generates 3D image information from the obtained first image information and the obtained second image information.
摘要翻译：提供三维（3D）照相机及其操作方法。 3D照相机包括：第一拍摄镜头单元; 第一图像传感器，其通过第一拍摄透镜单元获得物体的第一图像信息; 光束分割单元，设置在第一拍摄镜头单元和第一图像传感器之间的光路上，并且沿着第一图像传感器所在的第一路径沿着与第一路径不同的第二路径传播光; 设置在第二路径上的第二拍摄镜头单元; 第二图像传感器，其通过第一拍摄透镜单元和第二拍摄透镜获得对象的第二图像信息; 以及图像处理单元，其从所获得的第一图像信息和所获得的第二图像信息生成3D图像信息。

23. 发明授权

US08168800B2 Aβ-binding small molecules 有权
标题翻译： A＆bgr; - 结合的小分子
公开(公告)号：US08168800B2
公开(公告)日：2012-05-01
申请号：US12740329
申请日：2008-10-31
申请人： Lee-Way Jin , Kit S. Lam , Ruiwu Liu , Hyun-Seok Hong , Izumi Maezawa
发明人： Lee-Way Jin , Kit S. Lam , Ruiwu Liu , Hyun-Seok Hong , Izumi Maezawa
IPC分类号： C07D491/052
CPC分类号： C07D491/052 , A61K51/041 , A61K51/0453 , A61K51/0455 , A61K51/0463 , C07B2200/05
摘要： In one aspect, the present invention provides for compounds and labeled compounds of Formula I, and pharmaceutical compositions thereof. In another aspect, the present invention provides for methods of using compounds or labeled compounds of Formula I for various therapeutic and imaging purposes, including, but not limited to, treating Alzheimer's disease in patient and imaging Aβ peptide aggregates in a patient.
摘要翻译：一方面，本发明提供式I化合物和标记的化合物及其药物组合物。另一方面，本发明提供了使用式I化合物或标记化合物用于各种治疗和成像目的的方法，包括但不限于在患者和成像中治疗阿尔茨海默氏病A＆bgr; 肽聚集体在患者体内。

24. 发明申请

US20120052641A1 Methods of Manufacturing MOS Transistors 审中-公开
标题翻译：制造MOS晶体管的方法
公开(公告)号：US20120052641A1
公开(公告)日：2012-03-01
申请号：US13217871
申请日：2011-08-25
申请人： Hye-Lan Lee , Sangjin Hyun , Yugyun Shin , Hongbae Park , Huyong Lee , Hyung-seok Hong
发明人： Hye-Lan Lee , Sangjin Hyun , Yugyun Shin , Hongbae Park , Huyong Lee , Hyung-seok Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/823842 , H01L29/161 , H01L29/4236 , H01L29/42364 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench.
摘要翻译：提供制造MOS晶体管的方法。所述方法可以包括形成第一和第二沟槽。所述方法还可以包括在第一和第二沟槽的部分内形成第一金属图案。所述方法还可以包括从第二沟槽移除第一金属图案，同时至少部分第一金属图案保留在第一沟槽内。所述方法还可以包括在第一和第二沟槽内形成第二金属层，第二金属层形成在第一沟槽内的第一金属图案上。

25. 发明授权

US08117135B2 Concerned information recommendation system and method considering user's watching or listening time and maximum playing time of contents 有权
标题翻译：考虑用户观看或收听时间和内容最大播放时间的有关信息推荐系统和方法
公开(公告)号：US08117135B2
公开(公告)日：2012-02-14
申请号：US12325422
申请日：2008-12-01
申请人： Kwang-Seok Hong , Hyeong-Joon Kwon
发明人： Kwang-Seok Hong , Hyeong-Joon Kwon
IPC分类号： G06F15/18 , G06G7/00
CPC分类号： G06Q30/02
摘要： A user-concerned information recommendation system and method considering user's watching or listening time and the maximum playing time of contents are disclosed. The user-concerned information provision system includes a plurality of user terminals to provide contents transmitted from an external server to a user, a user-concerned information inference server to infer an association relationship between the contents based on information of maximum playing time and actual playing time of the contents provided to the user terminals, and a content provision server to provide a content requested by an arbitrary one of the user terminals and other contents associated with the requested content according to the inferred association relationship to the arbitrary one of the user terminals when receiving a request of the content from the arbitrary one of the user terminals, thereby providing more accurate user-concerned information to the user.
摘要翻译：公开了一种考虑用户观看或收听时间的用户相关信息推荐系统和方法以及内容的最大播放时间。用户关注信息提供系统包括：多个用户终端，用于提供从外部服务器向用户发送的内容;用户相关信息推断服务器，基于最大播放时间的信息和实际播放来推断内容之间的关联关系提供给用户终端的内容的时间;以及内容提供服务器，用于根据推断的关联关系向用户终端中的任意一个提供由任意一个用户终端请求的内容和与请求的内容相关联的其他内容当从任意一个用户终端接收到内容的请求时，从而向用户提供更准确的用户相关信息。

26. 发明授权

US08110830B2 Thin film transistor array substrate and method of manufacturing the same 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US08110830B2
公开(公告)日：2012-02-07
申请号：US12003626
申请日：2007-12-28
申请人： Joo Soo Lim , Hyun Seok Hong , Chang Bin Lee
发明人： Joo Soo Lim , Hyun Seok Hong , Chang Bin Lee
IPC分类号： H01L21/00 , H01L33/00
CPC分类号： H01L27/1288 , G02F1/136227 , G02F2001/136231 , G02F2001/136236 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： A thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern are disclosed. The TFT array substrate includes a gate line layer including a gate line formed on a substrate, a gate electrode diverging from the gate line, and a gate pad formed at the end of the gate line, a gate insulation film formed on the gate line layer, a semiconductor layer formed on the gate insulation film above the gate electrode, a data line layer including a data line intersecting the gate line, source and drain electrodes formed at opposite sides of the semiconductor layer, and a data pad formed at the end of the data line, a pixel electrode contacting the drain electrode, first and second oxidation preventing films contacting the gate pad and the data pad, and an at least two-layered passivation film deposited on the data line layer. The uppermost layer of the at least two-layered passivation film is formed at the remaining region excluding a region where the pixel electrode and the first and second oxidation preventing films are formed.
摘要翻译：一种薄膜晶体管（TFT）阵列基板及其制造方法，其能够减少曝光掩模的使用次数以减少处理时间和处理成本，并且过度地蚀刻光致抗蚀剂图案之下的钝化膜以容易地执行公开了光致抗蚀剂图案的剥离过程。 TFT阵列基板包括栅极线层，栅极线包括形成在基板上的栅极线，从栅极线发散的栅电极和形成在栅极线的端部的栅极焊盘，形成在栅极线层上的栅极绝缘膜形成在栅极电极上方的栅极绝缘膜上的半导体层，包括与栅极线交叉的数据线的数据线层，形成在半导体层的相对侧的源极和漏极;以及形成在栅极绝缘膜的末端的数据焊盘数据线，与漏电极接触的像素电极，与栅极焊盘和数据焊盘接触的第一和第二氧化防止膜以及沉积在数据线层上的至少两层钝化膜。至少两层钝化膜的最上层形成在除了形成像素电极和第一和第二氧化防止膜的区域之外的剩余区域。

27. 发明申请

US20110298129A1 STACKED PACKAGE 有权
标题翻译：堆叠包装
公开(公告)号：US20110298129A1
公开(公告)日：2011-12-08
申请号：US13093123
申请日：2011-04-25
申请人： Young-Seok Hong
发明人： Young-Seok Hong
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/3135 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/03 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4911 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06565 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/078 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A stacked package for an electronic device and a method of manufacturing the stacked package include a first semiconductor package being formed with a first conductive pad and a second conductive pad. A second semiconductor package is formed with a third conductive pad and a fourth conductive pad and is disposed over the first semiconductor package. A first conductive connecting member electrically connects the first conductive pad and the third conductive pad. A second conductive connection member electrically connects the second conductive pad and the fourth conductive pad.
摘要翻译：用于电子器件的堆叠封装和制造堆叠封装的方法包括形成有第一导电焊盘和第二导电焊盘的第一半导体封装。第二半导体封装形成有第三导电焊盘和第四导电焊盘，并且设置在第一半导体封装之上。第一导电连接部件电连接第一导电焊盘和第三导电焊盘。第二导电连接部件电连接第二导电焊盘和第四导电焊盘。

28. 发明授权

US08044469B2 Semiconductor device and associated methods 有权
标题翻译：半导体器件及相关方法
公开(公告)号：US08044469B2
公开(公告)日：2011-10-25
申请号：US12585313
申请日：2009-09-11
申请人： Hongbae Park , Hagju Cho , Sunghun Hong , Sangjin Hyun , Hoonjoo Na , Hyung-seok Hong
发明人： Hongbae Park , Hagju Cho , Sunghun Hong , Sangjin Hyun , Hoonjoo Na , Hyung-seok Hong
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/823857 , H01L27/0629 , H01L27/0805 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.
摘要翻译：一种半导体器件及相关方法，所述半导体器件包括具有第一阱区的半导体衬底，设置在第一阱区上的第一栅电极和第一N型封盖图案，第一P型封盖图案和第一栅极电介质图案，设置在第一阱区域和第一栅极电极之间。

29. 发明授权

US08026752B2 Delay circuit 有权
标题翻译：延时电路
公开(公告)号：US08026752B2
公开(公告)日：2011-09-27
申请号：US12494451
申请日：2009-06-30
申请人： Yun Seok Hong
发明人： Yun Seok Hong
IPC分类号： H03K3/289
CPC分类号： H03K5/1534
摘要： Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.
摘要翻译：公开了一种延迟电路。延迟电路包括脉冲发生单元，定时调整单元和脉冲宽度调节单元。脉冲发生单元被配置为响应于输入信号的上升沿产生具有预设宽度的脉冲信号。定时调整单元被配置为在预定时间过去之后响应于脉冲信号激活输出信号。脉冲宽度调整单元被配置为响应于输出信号的激活来调整输出信号的脉冲宽度。

30. 发明授权

US07972950B2 Method of fabricating semiconductor device having dual gate 有权
标题翻译：制造具有双栅极的半导体器件的方法
公开(公告)号：US07972950B2
公开(公告)日：2011-07-05
申请号：US12580302
申请日：2009-10-16
申请人： Hoon-joo Na , Yu-gyun Shin , Hong-bae Park , Hag-ju Cho , Sug-hun Hong , Sang-jin Hyun , Hyung-seok Hong
发明人： Hoon-joo Na , Yu-gyun Shin , Hong-bae Park , Hag-ju Cho , Sug-hun Hong , Sang-jin Hyun , Hyung-seok Hong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823828 , H01L21/28185 , H01L21/28194 , H01L21/32133 , H01L21/324 , H01L21/823437 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/51 , H01L29/517 , H01L29/518
摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.
摘要翻译：制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

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