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21. 发明申请

US20050003664A1 Method and apparatus for low temperature copper to copper bonding 有权
标题翻译：低温铜铜键合的方法和装置
公开(公告)号：US20050003664A1
公开(公告)日：2005-01-06
申请号：US10861030
申请日：2004-06-04
申请人： Shriram Ramanathan , Sarah Kim
发明人： Shriram Ramanathan , Sarah Kim
IPC分类号： H01L21/60 , H01L21/98 , H01L25/065 , H01L21/302 , H01L21/461
CPC分类号： H01L24/16 , H01L24/11 , H01L24/12 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13099 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/812 , H01L2224/81801 , H01L2224/81894 , H01L2224/8383 , H01L2224/9202 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/00014
摘要： A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.
摘要翻译：一种方法，包括：用导电材料涂覆在第一基板上的导电凸块以形成涂覆的导电凸块; 用导电材料在第二基板上涂覆导电凸块以形成涂覆的导电凸块; 以及将所述第一基板上的涂覆的导电凸块接合到所述第二基板上的所述涂覆的导电凸块上，以将所述第一基板电连接到所述第二基板。

22. 发明申请

US20070117348A1 3D integrated circuits using thick metal for backside connections and offset bumps 有权
标题翻译：使用厚金属的3D集成电路用于背面连接和偏移凸块
公开(公告)号：US20070117348A1
公开(公告)日：2007-05-24
申请号：US11284519
申请日：2005-11-21
申请人： Shriram Ramanathan , Sarah Kim , Patrick Morrow
发明人： Shriram Ramanathan , Sarah Kim , Patrick Morrow
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L24/94 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/14 , H01L2224/81 , H01L2924/00 , H01L2924/00014
摘要： Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.
摘要翻译：描述用于3D集成电路的背面连接及其制造方法。形成了在第二晶片上的第一晶片的堆叠，其具有位于堆叠顶部的第一晶片的衬底。第一晶片的衬底变薄。第一介电层沉积在薄的衬底上。在第一电介质层中形成有延伸穿过衬底至第一晶片的第一通孔。在第一通孔和第一介电层上沉积导电层以形成厚的导电线。在导电层上形成第二电介质层。延伸到导电线的第二通孔形成在第二电介质层中。延伸到第二通孔中并且抵消第一通孔的导电凸块形成在第二介电层上。

23. 发明申请

US20070111386A1 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices 审中-公开
公开(公告)号：US20070111386A1
公开(公告)日：2007-05-17
申请号：US11603521
申请日：2006-11-21
申请人： Sarah Kim , R. List , Scot Kellar
发明人： Sarah Kim , R. List , Scot Kellar
IPC分类号： H01L21/00
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76807 , H01L21/76898 , H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/8083 , H01L2224/80895 , H01L2224/81894 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/01079 , H01L2924/13091 , H01L2224/05552 , H01L2224/81 , H01L2224/83
摘要： A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

24. 发明申请

US20060076678A1 Thick metal layer integrated process flow to improve power delivery and mechanical buffering 审中-公开
标题翻译：厚金属层集成工艺流程，以改善动力传递和机械缓冲
公开(公告)号：US20060076678A1
公开(公告)日：2006-04-13
申请号：US11281709
申请日：2005-11-16
申请人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
发明人： Sarah Kim , Bob Martell , David Ayers , R. List , Peter Moon , Steven Towle , Anna George
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L21/76838 , H01L23/36 , H01L23/49816 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L24/11 , H01L24/16 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/05666 , H01L2224/13099 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014
摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
摘要翻译：在芯片或晶片级的受控崩溃芯片连接（C 4）凸起处制造具有一个或多个厚金属层的互连结构的工艺流程。互连结构可以用在微处理器的后端互连中。一个或多个集成的厚金属层可以改善功率传递并且降低在管芯/封装接口处的管芯的机械应力。

25. 发明申请

US20060055030A1 Using external radiators with electroosmotic pumps for cooling integrated circuits 有权
公开(公告)号：US20060055030A1
公开(公告)日：2006-03-16
申请号：US11270071
申请日：2005-11-09
申请人： Sarah Kim , R. List , James Maveety , Alan Myers , Quat Vu , Ravi Prasher , Ravi Mahajan , Gilroy Vandentop
发明人： Sarah Kim , R. List , James Maveety , Alan Myers , Quat Vu , Ravi Prasher , Ravi Mahajan , Gilroy Vandentop
IPC分类号： H01L23/34
CPC分类号： H01L23/473 , H01L2224/16 , H01L2224/73253 , H01L2224/82
摘要： An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

26. 发明申请

US20050101099A1 Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode 有权
标题翻译：使用纳米结构作为底部电极的片上去耦电容器的方法和器件
公开(公告)号：US20050101099A1
公开(公告)日：2005-05-12
申请号：US10420774
申请日：2003-04-23
申请人： Sarah Kim , Scot Kellar
发明人： Sarah Kim , Scot Kellar
IPC分类号： H01L21/02 , H01L23/50 , H01L27/08 , H01L21/20
CPC分类号： B82Y10/00 , H01L23/50 , H01L27/0805 , H01L28/84 , H01L2924/0002 , H05K1/162 , H05K2201/026 , Y10S977/72 , Y10S977/734 , Y10S977/784 , Y10S977/932 , H01L2924/00
摘要： Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
摘要翻译：用于片上去耦电容器的装置。电容器包括底部电极，其由沉积在平坦化金属上的纳米结构，沉积在纳米结构上的电介质材料和沉积在电介质材料上的顶部电极组成。通过调制纳米结构的直径和/或长度可以调节底部电极的形状，以增加电容，而不增加片上去耦电容器的占空比。

27. 发明申请

US20050059217A1 METHODS OF FORMING BACKSIDE CONNECTIONS ON A WAFER STACK 有权
标题翻译：在WAFER堆叠上形成背面连接的方法
公开(公告)号：US20050059217A1
公开(公告)日：2005-03-17
申请号：US10665824
申请日：2003-09-17
申请人： Patrick Morrow , R. List , Sarah Kim
发明人： Patrick Morrow , R. List , Sarah Kim
IPC分类号： H01L21/768 , H01L21/98 , H01L23/48 , H01L25/065 , H01L21/30 , H01L21/46
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13025 , H01L2224/13111 , H01L2224/13147 , H01L2224/2919 , H01L2224/8182 , H01L2225/06513 , H01L2225/06541 , H01L2924/01079 , H01L2924/00014 , H01L2924/01082
摘要： Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.
摘要翻译：公开了在晶片叠层上形成背面连接的各种方法。为了形成背面连接，通孔形成在要与第二晶片结合的第一晶片中。用于背面连接的通路与互连结构一起形成在第一晶片的一侧，并且使用这些通孔在第一晶片的相对侧上形成背面连接。

28. 发明申请

US20050003652A1 Method and apparatus for low temperature copper to copper bonding 审中-公开
公开(公告)号：US20050003652A1
公开(公告)日：2005-01-06
申请号：US10746582
申请日：2003-12-24
申请人： Shriram Ramanathan , Sarah Kim
发明人： Shriram Ramanathan , Sarah Kim
IPC分类号： H01L21/60 , H01L21/98 , H01L25/065 , H01L21/44
CPC分类号： H01L24/16 , H01L24/11 , H01L24/12 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13099 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/812 , H01L2224/81801 , H01L2224/81894 , H01L2224/8383 , H01L2224/9202 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/00014
摘要： A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.

29. 发明授权

US07063938B2 Method of preparing patterned colloidal crystals 失效
标题翻译：制备图案化胶体晶体的方法
公开(公告)号：US07063938B2
公开(公告)日：2006-06-20
申请号：US10662088
申请日：2003-09-12
申请人： Seung-Man Yang , Ki-Ra Yi , Yong- Hak Park , Sarah Kim
发明人： Seung-Man Yang , Ki-Ra Yi , Yong- Hak Park , Sarah Kim
IPC分类号： G03F7/00 , B01J13/00
CPC分类号： G03F7/0005 , B82Y20/00 , C30B29/60 , G02B6/1225
摘要： A method of preparing patterned colloidal crystals includes filling a monomer solution in the interstices between particles of planar colloidal crystals for photopolymerization inside them, and performing a selective photopolymerization process between the colloidal crystals using a mask. In one exemplary method, a first monomer solution for photopolymerization is filled inside planar colloidal crystals. A first selective photopolymerization process is performed inside the colloidal crystals using a mask. A second monomer solution for photopolymerization is filled into the firstly patterned colloidal crystals. At least one additional photopolymerization process is performed inside the firstly patterned colloidal crystals using an additional mask. Through this method, colloidal crystalline regions oriented in the same direction with different refractive indexes can be controlled in a level of μm. Further, repeated patterns can be inexpensively and easily prepared.
摘要翻译：制备图案化胶态晶体的方法包括将单体溶液填充在其内的光致聚合的平面胶体晶体的颗粒之间的间隙中，并使用掩模在胶体晶体之间进行选择性光聚合过程。在一个示例性方法中，用于光聚合的第一单体溶液填充在平面胶体晶体内。使用掩模在胶体晶体内进行第一选择性光聚合方法。用于光聚合的第二单体溶液被填充到首先构图的胶体晶体中。使用附加的掩模在第一图案化胶体晶体内进行至少一个额外的光聚合过程。通过该方法，可以将具有不同折射率的相同方向取向的胶体结晶区域控制在一定程度上。此外，可以廉价且容易地制备重复的图案。

30. 发明申请

US20050170759A1 Differential planarization 失效
公开(公告)号：US20050170759A1
公开(公告)日：2005-08-04
申请号：US11055453
申请日：2005-02-02
申请人： James Boardman , Sarah Kim , Paul Fischer , Mauro Kobrinsky
发明人： James Boardman , Sarah Kim , Paul Fischer , Mauro Kobrinsky
IPC分类号： H01L21/768 , B24B1/00
CPC分类号： H01L21/7684 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.

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