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21. 发明申请

US20100230751A1 SELF-ALIGNED SCHOTTKY DIODE 有权
标题翻译：自对准肖特基二极管
公开(公告)号：US20100230751A1
公开(公告)日：2010-09-16
申请号：US12538213
申请日：2009-08-10
申请人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7839 , H01L21/26586 , H01L29/665 , H01L29/66643 , H01L29/66659
摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.
摘要翻译：肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构另一侧的掺杂保护环。肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。还提供了用于本发明的肖特基势垒二极管的设计结构。

22. 发明授权

US07691734B2 Deep trench based far subcollector reachthrough 失效
标题翻译：深沟渠远极子集线器达到
公开(公告)号：US07691734B2
公开(公告)日：2010-04-06
申请号：US11680637
申请日：2007-03-01
申请人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译：通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

23. 发明申请

US20100038750A1 Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors 有权
标题翻译：具有VIAS和高密度电容器的结构，设计结构和制造方法
公开(公告)号：US20100038750A1
公开(公告)日：2010-02-18
申请号：US12191385
申请日：2008-08-14
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang Ile , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang Ile , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L29/92 , G06F17/50
CPC分类号： H01L29/66181 , H01L29/945
摘要： A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.
摘要翻译：半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

24. 发明申请

US20090179272A1 DOUBLE GATE DEPLETION MODE MOSFET 有权
标题翻译：双栅极截止模式MOSFET
公开(公告)号：US20090179272A1
公开(公告)日：2009-07-16
申请号：US11972811
申请日：2008-01-11
申请人： John B. Campi, JR. , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： John B. Campi, JR. , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/26586 , H01L29/0653 , H01L29/0688 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。底部电极层垂直邻接体层并向身体层提供电偏压。顶部电极和源极和漏极区域形成在主体层上。选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。

25. 发明授权

US07538409B2 Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US07538409B2
公开(公告)日：2009-05-26
申请号：US11422690
申请日：2006-06-07
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

26. 发明授权

US07518215B2 One mask hyperabrupt junction varactor using a compensated cathode contact 有权
标题翻译：一个掩模超破坏结变容二极管使用补偿阴极接触
公开(公告)号：US07518215B2
公开(公告)日：2009-04-14
申请号：US10905486
申请日：2005-01-06
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.
摘要翻译：公开了一种半导体结构，其包括具有补偿的阴极接触的超级连接变容二极管及其制造方法。该方法包括用于形成子集电极/阴极，集电极/阱和超破裂结的单个注入掩模。

27. 发明授权

US07494912B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

28. 发明申请

US20080211064A1 DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH 失效
标题翻译：深度基础的FAR SUBCOLLECTOR REACHTHROUGH
公开(公告)号：US20080211064A1
公开(公告)日：2008-09-04
申请号：US11680637
申请日：2007-03-01
申请人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L29/06 , H01L21/425
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译：通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。穿通区可以形成在至少一个深沟槽周围，或仅在至少一个深沟槽的一侧上。如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

29. 发明申请

US20080122574A1 POLYSILICON CONTAINING RESISTOR WITH ENHANCED SHEET RESISTANCE PRECISION AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：具有增强型电阻精度的多晶硅电容器及其制造方法
公开(公告)号：US20080122574A1
公开(公告)日：2008-05-29
申请号：US11458494
申请日：2006-07-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , John E. Florkey , Robert M. Rassel , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , John E. Florkey , Robert M. Rassel , Kunal Vaed
IPC分类号： H01C1/06 , H01L21/20
CPC分类号： H01L27/0802 , H01L21/26513 , H01L28/20
摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.
摘要翻译：含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

30. 发明授权

US07285472B2 Low tolerance polysilicon resistor for low temperature silicide processing 失效
标题翻译：用于低温硅化物处理的低容差多晶硅电阻器
公开(公告)号：US07285472B2
公开(公告)日：2007-10-23
申请号：US10905940
申请日：2005-01-27
申请人： Douglas D. Coolbaugh , John E. Florkey , Robert M. Rassel
发明人： Douglas D. Coolbaugh , John E. Florkey , Robert M. Rassel
IPC分类号： H01L21/8222
CPC分类号： H01L21/26513 , H01L27/0802 , H01L28/20
摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.
摘要翻译：提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。激活可以通过沉积保护性介电层或单独的激活退火来进行。在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

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