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21. 发明授权

US07065635B1 Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor 有权
标题翻译：用于处理无序多问题多链处理器中条件码修改器的方法
公开(公告)号：US07065635B1
公开(公告)日：2006-06-20
申请号：US10738576
申请日：2003-12-17
申请人： Rabin A. Sugumar , Sorin Iacobovici , Chandra M. R. Thimmannagari
发明人： Rabin A. Sugumar , Sorin Iacobovici , Chandra M. R. Thimmannagari
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.
摘要翻译：一种用于处理无序多股处理器中的条件代码修改指令的技术包括为每条链提供条件代码体系结构寄存器文件，提供条件代码工作寄存器文件，以及分配条件码架构寄存器文件识别信息（ CARF_ID）和条件代码工作寄存器文件识别信息（CWRF_ID）到条件代码修改指令。 CARF_ID用于索引存储CWRF_ID的条件代码重命名表中的位置。此后，在条件代码修改指令的无异常执行时，执行结果从条件代码工作寄存器文件复制到依赖于CARF_ID，CWRF_ID，寄存器类型信息和链标识信息的条件代码架构寄存器文件。

22. 发明授权

US08537828B2 Scalable interface for connecting multiple computer systems which performs parallel MPI header matching 有权
标题翻译：用于连接执行并行MPI头匹配的多个计算机系统的可扩展接口
公开(公告)号：US08537828B2
公开(公告)日：2013-09-17
申请号：US13489496
申请日：2012-06-06
申请人： Rabin A. Sugumar , Lars Paul Huse , Bjørn Dag Johnsen
发明人： Rabin A. Sugumar , Lars Paul Huse , Bjørn Dag Johnsen
IPC分类号： H04L12/28
CPC分类号： G06F15/17337
摘要： An interface device for a compute node in a computer cluster which performs Message Passing Interface (MPI) header matching using parallel matching units. The interface device comprises a memory that stores posted receive queues and unexpected queues. The posted receive queues store receive requests from a process executing on the compute node. The unexpected queues store headers of send requests (e.g., from other compute nodes) that do not have a matching receive request in the posted receive queues. The interface device also comprises a plurality of hardware pipelined matcher units. The matcher units perform header matching to determine if a header in the send request matches any headers in any of the plurality of posted receive queues. Matcher units perform the header matching in parallel. In other words, the plural matching units are configured to search the memory concurrently to perform header matching.
摘要翻译：用于计算机集群中的计算节点的接口设备，其使用并行匹配单元执行消息传递接口（MPI）报头匹配。接口设备包括存储发布的接收队列和意外队列的存储器。发布的接收队列存储在计算节点上执行的进程的接收请求。意外队列存储在发布的接收队列中不具有匹配的接收请求的发送请求（例如来自其他计算节点）的头部。接口设备还包括多个硬件流水线匹配器单元。匹配器单元执行报头匹配以确定发送请求中的报头是否匹配多个发布的接收队列中的任何一个中的任何报头。匹配器单元并行执行头匹配。换句话说，多个匹配单元被配置为同时搜索存储器以执行头匹配。

23. 发明申请

US20100332908A1 Performing Remote Loads and Stores over Networks 有权
标题翻译：通过网络执行远程负载和存储
公开(公告)号：US20100332908A1
公开(公告)日：2010-12-30
申请号：US12495400
申请日：2009-06-30
申请人： Bjorn Dag Johnsen , Rabin A. Sugumar , Ola Torudbakken
发明人： Bjorn Dag Johnsen , Rabin A. Sugumar , Ola Torudbakken
IPC分类号： G06F15/16 , G06F15/167 , G06F11/30
CPC分类号： H04L12/6418
摘要： A network adaptor which performs CPU loads and stores to remote memory over network fabrics. The network adaptor receives a transfer request from a compute node and converts the request to a remote transfer request, which is transmitted to the network. The network adaptor then monitors the network connection for a remote completion response. When the network adaptor receives the remote completion response within a specific time period, the network adaptor transmits a first completion response to the compute node. If the network adaptor does not receive the remote completion response within the specific time period, the network adaptor transmits an “early completion response” to the compute node. The network adaptor continues to monitor for the actual response. This allows the compute node to continue processing without having to wait for the actual response to be received. The method handles small payloads efficiently and also accounts for long completion delays.
摘要翻译：网络适配器，通过网络结构执行CPU加载和存储到远程内存。网络适配器从计算节点接收传输请求，并将请求转换为传输到网络的远程传输请求。然后，网络适配器监视网络连接以进行远程完成响应。当网络适配器在特定时间段内接收到远程完成响应时，网络适配器向计算节点发送第一完成响应。如果网络适配器在特定时间段内没有收到远程完成响应，则网络适配器向计算节点发送“早期完成响应”。网络适配器继续监视实际响应。这允许计算节点继续处理，而不必等待接收到实际响应。该方法可以有效地处理小型有效载荷，并且也会导致长时间完成延迟

24. 发明授权

US07543132B1 Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes 有权
标题翻译：在具有多页尺寸的高线程处理器中优化硬件TLB重新载入性能
公开(公告)号：US07543132B1
公开(公告)日：2009-06-02
申请号：US10880985
申请日：2004-06-30
申请人： Greg F. Grohoski , Ashley Saulsbury , Paul J. Jordan , Manish Shah , Rabin A. Sugumar , Mark Debbage , Venkatesh Iyengar
发明人： Greg F. Grohoski , Ashley Saulsbury , Paul J. Jordan , Manish Shah , Rabin A. Sugumar , Mark Debbage , Venkatesh Iyengar
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0817 , G06F12/0897 , G06F2212/652 , G06F2212/654 , G06F2212/684
摘要： A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a predictor array to predict the TSB page size. In one embodiment of the invention, the predictor array comprises two-bit saturating up-down counters that are used to enhance the accuracy of the TSB prediction. The saturating up-down counters are configured to avoid making rapid changes in the TSB prediction upon detection of an error. Multiple misses occur before the prediction output is changed. The page size specified by the predictor index is searched first. Using the technique described herein, errors are minimized because the counter leads to the correct result at least half the time.
摘要翻译：一种用于在多线程，多核处理器中重新加载翻译后备缓冲器的性能的方法和装置。通过散列多个数据参数并生成作为预测器阵列的输入提供的索引来预测TSB页面大小来实现TSB预测。在本发明的一个实施例中，预测器阵列包括用于增强TSB预测精度的二位饱和上拉计数器。饱和上拉计数器配置为避免在检测到错误时对TSB预测进行快速更改。在预测输出改变之前会发生多重错误。首先搜索由预测变量索引指定的页面大小。使用本文描述的技术，误差被最小化，因为计数器至少在一半的时间内导致正确的结果。

25. 发明授权

US07373489B1 Apparatus and method for floating-point exception prediction and recovery 有权
标题翻译：浮点异常预测和恢复的装置和方法
公开(公告)号：US07373489B1
公开(公告)日：2008-05-13
申请号：US10880713
申请日：2004-06-30
申请人： Jeffrey S. Brooks , Paul J. Jordan , Rabin A. Sugumar
发明人： Jeffrey S. Brooks , Paul J. Jordan , Rabin A. Sugumar
IPC分类号： G06F9/00 , G06F7/38 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/3828 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.
摘要翻译：一种用于浮点异常预测和恢复的装置和方法。在一个实施例中，处理器可以包括指令提取逻辑，其被配置为从多个线程中的一个发出第一指令，并且从多个线程中的另一个线程连续地发出第二指令。处理器还可以包括浮点算术逻辑，其被配置为执行由指令提取逻辑从多个线程中的给定一个发出的浮点指令，并且还被配置为确定浮点指令是否生成异常，以及还可以包括被配置为预测浮点指令是否将产生异常的异常预测逻辑，其中在浮点运算逻辑确定浮点指令是否产生异常之前发生预测。

26. 发明授权

US07350053B1 Software accessible fast VA to PA translation 有权
标题翻译：软件可访问快速VA到PA翻译
公开(公告)号：US07350053B1
公开(公告)日：2008-03-25
申请号：US11034345
申请日：2005-01-11
申请人： Rabin A. Sugumar , Robert T. Golla , Paul J. Jordan
发明人： Rabin A. Sugumar , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/1081 , G06F12/1027
摘要： A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.
摘要翻译：公开了一种用于传送数据的方法，其包括将虚拟地址传送到翻译后备缓冲器（TLB）并将虚拟地址转换为计算机存储器的物理地址。该方法还包括将由TLB转换的物理地址加载到处理器内的寄存器中，并将数据从物理地址传输到目标计算设备。

27. 发明授权

US5913069A Interleaving memory in distributed vector architecture multiprocessor system 失效
标题翻译：在分布式向量架构多处理器系统中交织内存
公开(公告)号：US5913069A
公开(公告)日：1999-06-15
申请号：US987948
申请日：1997-12-10
申请人： Rabin A. Sugumar , Stefanos Kaxiras
发明人： Rabin A. Sugumar , Stefanos Kaxiras
IPC分类号： G06F15/78 , G06F15/80 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8076 , G06F15/8084
摘要： A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.
摘要翻译：矢量/标量计算机系统具有通过互连网络互连的节点。每个节点包括向量执行单元，标量执行单元，物理向量寄存器和存储器。来自节点的物理矢量寄存器一起形成一个架构向量寄存器，它是矢量应用的参考。来自节点的记忆一起形成聚合记忆。矢量应用将存储器矢量元素从存储器加载到物理矢量寄存器，并将物理矢量元素从物理矢量寄存器存储到存储器。存储器矢量元素在节点的存储器之间进行交织，以减少负载和存储期间的节点间流量。

28. 发明授权

US08782161B2 Method and system for offloading computation flexibly to a communication adapter 有权
标题翻译：用于将计算灵活卸载到通信适配器的方法和系统
公开(公告)号：US08782161B2
公开(公告)日：2014-07-15
申请号：US13173473
申请日：2011-06-30
申请人： Rabin A. Sugumar , David Brower
发明人： Rabin A. Sugumar , David Brower
IPC分类号： G06F15/167
CPC分类号： G06F9/5027 , G06F2209/509
摘要： A method for offloading computation flexibly to a communication adapter includes receiving a message that includes a procedure image identifier associated with a procedure image of a host application, determining a procedure image and a communication adapter processor using the procedure image identifier, and forwarding the first message to the communication adapter processor configured to execute the procedure image. The method further includes executing, on the communication adapter processor independent of a host processor, the procedure image in communication adapter memory by acquiring a host memory latch for a memory block in host memory, reading the memory block in the host memory after acquiring the host memory latch, manipulating, by executing the procedure image, the memory block in the communication adapter memory to obtain a modified memory block, committing the modified memory block to the host memory, and releasing the host memory latch.
摘要翻译：一种用于将计算灵活地卸载到通信适配器的方法包括接收包括与主机应用程序的过程映像相关联的过程映像标识符的消息，使用过程映像标识符确定过程映像和通信适配器处理器，以及转发第一消息配置为执行过程映像的通信适配器处理器。该方法还包括通过获取主机存储器中的存储器块的主机存储器锁存器来在独立于主处理器的通信适配器处理器上执行通信适配器存储器中的过程映像，在获取主机之后读取主机存储器中的存储器块存储器锁存器，通过执行过程映像来操纵通信适配器存储器中的存储块，以获得修改的存储器块，将修改的存储器块提交到主机存储器，以及释放主机存储器锁存器。

29. 发明申请

US20100332789A1 Network Use of Virtual Addresses Without Pinning or Registration 有权
标题翻译：虚拟地址的网络使用，无需固定或注册
公开(公告)号：US20100332789A1
公开(公告)日：2010-12-30
申请号：US12495805
申请日：2009-06-30
申请人： Rabin A. Sugumar , Robert W. Wittosch , Bjørn Dag Johnsen , William M. Ortega
发明人： Rabin A. Sugumar , Robert W. Wittosch , Bjørn Dag Johnsen , William M. Ortega
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081
摘要： A system comprising a compute node and coupled network adapter (NA) that allows the NA to directly use CPU virtual addresses without pinning pages in system memory. The NA performs memory accesses in response to requests from various sources. Each request source is assigned to context. Each context has a descriptor that controls the address translation performed by the NA. When the CPU wants to update translation information it sends a synchronization request to the NA that causes the NA to stop fetching a category of requests associated with the information update. The category may be requests associated with a context or a page address. Once the NA determines that all the fetched requests in the category have completed it notifies the CPU and the CPU performs the information update. Once the update is complete, the CPU clears the synchronization request and the NA starts fetching requests in the category.
摘要翻译：一种包括计算节点和耦合网络适配器（NA）的系统，其允许NA直接使用CPU虚拟地址而不在系统存储器中固定页面。 NA响应来自各种来源的请求，执行存储器访问。每个请求源被分配给上下文。每个上下文都有一个描述符，用于控制由NA执行的地址转换。当CPU要更新翻译信息时，它向NA发送同步请求，导致NA停止获取与信息更新相关联的一类请求。类别可以是与上下文或页面地址相关联的请求。一旦NA确定类别中的所有获取的请求已经完成，它通知CPU并且CPU执行信息更新。更新完成后，CPU将清除同步请求，NA将开始获取该类别中的请求。

30. 发明申请

US20100332612A1 Caching Data in a Cluster Computing System Which Avoids False-Sharing Conflicts 有权
标题翻译：将数据缓存在避免虚假共享冲突的群集计算系统中
公开(公告)号：US20100332612A1
公开(公告)日：2010-12-30
申请号：US12495635
申请日：2009-06-30
申请人： Bjorn Dag Johnsen , Rabin A. Sugumar , Ben Sum , Lars Paul Huse
发明人： Bjorn Dag Johnsen , Rabin A. Sugumar , Ben Sum , Lars Paul Huse
IPC分类号： G06F15/167 , G06F12/08
CPC分类号： G06F12/0817 , G06F12/0813
摘要： Managing operations in a first compute node of a multi-computer system. A remote write may be received to a first address of a remote compute node. A first data structure entry may be created in a data structure, which may include the first address and status information indicating that the remote write has been received. Upon determining that the local cache of the first compute node has been updated with the remote write, the remote write may be issued to the remote compute node. Accordingly, the first data structure entry may be released upon completion of the remote write.
摘要翻译：在多计算机系统的第一个计算节点中管理操作。远程写入可以被接收到远程计算节点的第一地址。可以在数据结构中创建第一数据结构条目，数据结构可以包括指示已经接收到远程写入的第一地址和状态信息。在确定使用远程写入更新了第一计算节点的本地高速缓存之后，可以向远程计算节点发出远程写入。因此，可以在完成远程写入时释放第一数据结构条目。

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