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21. 发明授权

US5887036A Logical block for a Viterbi decoder 失效
标题翻译：维特比解码器的逻辑块
公开(公告)号：US5887036A
公开(公告)日：1999-03-23
申请号：US729672
申请日：1996-10-03
申请人： Miodrag Temerinac
发明人： Miodrag Temerinac
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/12
CPC分类号： H03M13/6362 , H03M13/41 , H03M13/6502
摘要： A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.
摘要翻译：公开了用于对由卷积码编码的数据序列进行解码的逻辑块，其中给定数量的状态将被评估。这些给定状态被分配给存储相关联路径和累积距离值的给定数量的状态存储器。给定数量的状态存储器与并行处理块相关联，并行处理块各自具有作为要并行处理的最小组，要从第一和第二并行处理块读取的两个状态存储器和要写入第三和第二并行处理块的两个状态存储器第四并行处理块。最佳的内存组织允许简单的并行处理和降低电路复杂度。

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