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21. 发明授权

US09841780B2 Apparatus and method for producing a report including a subset of a plurality of active timers based on a query to accurate quality of service based on the report 有权
公开(公告)号：US09841780B2
公开(公告)日：2017-12-12
申请号：US14324352
申请日：2014-07-07
申请人： Ron-Michael Bar , Eran Glickman , Amir David Modan
发明人： Ron-Michael Bar , Eran Glickman , Amir David Modan
IPC分类号： G06F1/04 , G06F1/14 , G06F17/30 , H04L1/18 , G06F9/44
CPC分类号： G06F1/14 , G06F9/451 , G06F17/30979 , H04L1/1883
摘要： An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.

22. 发明授权

US09400654B2 System on a chip with managing processor and method therefor 有权
标题翻译：具有管理处理器及其方法的芯片上的系统
公开(公告)号：US09400654B2
公开(公告)日：2016-07-26
申请号：US14316876
申请日：2014-06-27
申请人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Stas Yosupov
发明人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Stas Yosupov
IPC分类号： G06F9/30 , G06F11/30
CPC分类号： G06F9/30145 , G06F11/3024 , G06F11/3055 , G06F11/3433 , G06F2201/86 , G06F2201/87
摘要： A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.
摘要翻译：芯片上的系统包括用于控制芯片上的系统的操作的管理处理器。管理处理器包括核心监视器控制逻辑电路，其可操作以：接收至少一个指令; 确定指令是否是激活指令; 确定管理处理器是处于或转换到空闲状态; 以及响应于作为激活指令的指令并且所述管理处理器处于或转换到空闲状态，将所述管理处理器从第一操作模式转换到第二操作模式。

23. 发明授权

US09330024B1 Processing device and method thereof 有权
标题翻译：处理装置及其方法
公开(公告)号：US09330024B1
公开(公告)日：2016-05-03
申请号：US14510493
申请日：2014-10-09
申请人： Eran Glickman , Nir Atzmon , Ron-Michael Bar , Benny Michalovich
发明人： Eran Glickman , Nir Atzmon , Ron-Michael Bar , Benny Michalovich
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F2212/1016 , G06F2212/1041 , G06F2212/152 , G06F2212/608 , G06F2212/65
摘要： A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral.A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.
摘要翻译：处理装置尤其包括单片存储器累加器单元，其将虚拟存储器空间暴露给互连总线，并且包括具有翻译信息的转换表，以将具有虚拟地址的请求转换为具有物理地址的请求。 MMA被配置为接收交易请求; 将接收到的请求的地址转换成物理地址; 并将交易请求传递到集成外围设备的存储位置。处理设备包括至少一个具有可访问性适配器单元的集成外围设备IP，AA将虚拟存储器空间暴露给互连总线650，并且其包括具有转换信息的转换表。 AA 150被配置为接收交易请求; 将接收到的请求的地址转换成物理地址; 并将交易请求路由到IP的存储位置。

24. 发明申请

US20160103769A1 PROCESSING DEVICE AND METHOD THEREOF 有权
标题翻译：处理装置及其方法
公开(公告)号：US20160103769A1
公开(公告)日：2016-04-14
申请号：US14510493
申请日：2014-10-09
申请人： ERAN GLICKMAN , NIR ATZMON , RON-MICHAEL BAR , BENNY MICHALOVICH
发明人： ERAN GLICKMAN , NIR ATZMON , RON-MICHAEL BAR , BENNY MICHALOVICH
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F2212/1016 , G06F2212/1041 , G06F2212/152 , G06F2212/608 , G06F2212/65
摘要： A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral.A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.
摘要翻译：处理装置尤其包括单片存储器累加器单元，其将虚拟存储器空间暴露给互连总线，并且包括具有翻译信息的转换表，以将具有虚拟地址的请求转换为具有物理地址的请求。 MMA被配置为接收交易请求; 将接收到的请求的地址转换成物理地址; 并将交易请求传递到集成外围设备的存储位置。处理设备包括至少一个具有可访问性适配器单元的集成外围设备IP，AA将虚拟存储器空间暴露给互连总线650，并且其包括具有转换信息的转换表。 AA 150被配置为接收交易请求; 将接收到的请求的地址转换成物理地址; 并将交易请求路由到IP的存储位置。

25. 发明申请

US20150242343A1 SYSTEM ON CHIP AND METHOD OF OPERATING A SYSTEM ON CHIP 有权
标题翻译：芯片系统和操作芯片系统的方法
公开(公告)号：US20150242343A1
公开(公告)日：2015-08-27
申请号：US14190374
申请日：2014-02-26
申请人： NIR ATZMON , RON-MICHAEL BAR , ERAN GLICKMAN , BENNY MICHALOVICH
发明人： NIR ATZMON , RON-MICHAEL BAR , ERAN GLICKMAN , BENNY MICHALOVICH
IPC分类号： G06F13/16 , G11C7/10 , G06F13/32 , G06F12/02
CPC分类号： G06F13/1673 , G06F13/32
摘要： A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers.A method of operating a system on chip is also described.
摘要翻译：包括两个或多个数据源的片上系统SoC，存储器单元，存储器控制单元和处理单元。每个数据源都能够提供数据流。存储器控制单元被布置为为每个数据流保持存储器单元中的缓冲器，并且经由相应的缓冲器将相应的数据流路由到处理单元。每个缓冲器具有可变的并且至少包括相应缓冲器的空闲存储器的量的缓冲器特性。存储器控制单元被配置为根据各个缓冲器的缓冲器特性来分配和分配每个缓冲器的存储器区域，从而允许在缓冲器中重新分配存储器单元的存储器。还描述了一种操作片上系统的方法。

26. 发明授权

US08249177B2 Detection of frame marker quality 失效
标题翻译：检测帧标记质量
公开(公告)号：US08249177B2
公开(公告)日：2012-08-21
申请号：US12397790
申请日：2009-03-04
申请人： Etai Adar , Michael Bar-Joshua , David Stauffer
发明人： Etai Adar , Michael Bar-Joshua , David Stauffer
IPC分类号： H04L27/00
CPC分类号： H04L7/042 , H04L1/20 , H04L7/046
摘要： For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.
摘要翻译：例如，检测帧标记质量的方法包括：在从第一分量发送到公共硬件单元的第二分量的比特流中检测具有不同于由通信协议; 以及基于所述位模式和所述未损坏帧标记的位模式之间的差异，将质量水平指示符分配给帧标记。

27. 发明授权

US07904865B2 Placement driven routing 有权
标题翻译：放置驱动路由
公开(公告)号：US07904865B2
公开(公告)日：2011-03-08
申请号：US12018422
申请日：2008-01-23
申请人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
发明人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).
摘要翻译：一种根据集成电路规范布置布线的方法来创建集成电路设计。一旦初始放置的设计合法化，而不仅仅是启动布线路由，该方法可以识别集成电路设计中包含阻塞项目的书籍。该方法允许临时暂停路由进程，并将项目移动到一定程度。该移动过程被控制（根据相关书籍的信号功率输出而限制），使得集成电路设计的时序不受任何这种“中间路由”移动的影响。如果这些书没有任何封闭的物品，该过程将继续在物品和书籍之间布线。如果在电线路由之前或期间的任何一点，发现这些书籍确实有阻塞的项目，该过程将暂停线路的路由并执行任意数量的不同进程来解决阻塞的项目情况（解除阻塞的项目）。

28. 发明申请

US20090187683A1 ADAPTIVE LINK WIDTH CONTROL 审中-公开
标题翻译：自适应链路宽度控制
公开(公告)号：US20090187683A1
公开(公告)日：2009-07-23
申请号：US12017735
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F3/00
CPC分类号： H04L47/10 , H04L47/2416
摘要： A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption.
摘要翻译：通信装置使用至少一个逻辑通信链路，其包括计算机化的硬件设备内的多条通道。数据传输监视器连接到逻辑通信链路，并测量逻辑通信链路的实时数据传输带宽。此外，链路管理单元或链路宽度控制单元（比较器）连接到通道和数据传输监视器，并将实时数据传输带宽连续地与预定的数据传输带宽标准进行比较。如果实时数据传输带宽低于预定的数据传输带宽标准，则链路管理单元适于通过激活附加通道来执行逻辑通信链路的上配置，最多数目的通道组成逻辑通信链路。相反，如果实时数据传输带宽高于预定的数据传输带宽标准，则链路管理单元适于通过停用逻辑通信链路内的通道来执行逻辑通信链路的下配置。当通道相对于通道被激活时，通道消耗较少的功率，因此下配置降低功耗。

29. 发明申请

US20090177822A1 Device, System, and Method of Handling Transactions 有权
标题翻译：设备，系统和处理交易的方法
公开(公告)号：US20090177822A1
公开(公告)日：2009-07-09
申请号：US11969475
申请日：2008-01-04
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/362
摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.
摘要翻译：一些实施例包括例如处理事务的设备，系统和方法。在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

30. 发明申请

US20080247316A1 Method Circuit and System for Data Flow Control 审中-公开
标题翻译：数据流控制方法电路与系统
公开(公告)号：US20080247316A1
公开(公告)日：2008-10-09
申请号：US11695681
申请日：2007-04-03
申请人： Michael Bar-Joshua , Bruce Leroy Beukema , Alexander Mesh , Shaul Yifrach
发明人： Michael Bar-Joshua , Bruce Leroy Beukema , Alexander Mesh , Shaul Yifrach
IPC分类号： H04N5/91
CPC分类号： H04N21/23406 , H04N7/17327 , H04N21/44004 , H04N21/6377 , H04N21/6583
摘要： Disclosed is a method and circuit for a receiver to receive data from an associated data transmitter. The receiver may include a signaling module adapted to transmit a Ready-To-Receive (“RTR”) signal to the associated transmitter when a number of vacant bits in a data buffer exceeds a delay associated value.
摘要翻译：公开了一种用于接收机从相关联的数据发射机接收数据的方法和电路。接收机可以包括适配成当数据缓冲器中的空闲位数超过延迟相关值时向相关联的发射机发送就绪接收（“RTR”）信号的信令模块。

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