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21. 发明授权

US08710485B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08710485B2
公开(公告)日：2014-04-29
申请号：US13458042
申请日：2012-04-27
申请人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
发明人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
IPC分类号： H01L29/06 , H01L47/00
CPC分类号： H01L21/823431 , H01L27/101 , H01L27/1211 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.
摘要翻译：根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。

22. 发明授权

US08518769B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08518769B2
公开(公告)日：2013-08-27
申请号：US13415592
申请日：2012-03-08
申请人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka
发明人： Kensuke Ota , Toshinori Numata , Masumi Saitoh , Chika Tanaka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/786 , H01L29/00 , H01L29/785 , H01L29/78696
摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.
摘要翻译：实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

23. 发明授权

US08492219B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08492219B2
公开(公告)日：2013-07-23
申请号：US13487295
申请日：2012-06-04
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L21/8234 , H01L21/337 , H01L21/8232 , H01L21/336 , H01L21/00
CPC分类号： H01L27/0207 , H01L21/266 , H01L21/823437 , H01L21/823462 , H01L21/845 , H01L27/1211 , H01L29/66628 , H01L29/785
摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
摘要翻译：在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

24. 发明申请

US20120299100A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120299100A1
公开(公告)日：2012-11-29
申请号：US13415592
申请日：2012-03-08
申请人： Kensuke OTA , Toshinori NUMATA , Masumi SAITOH , Chika TANAKA
发明人： Kensuke OTA , Toshinori NUMATA , Masumi SAITOH , Chika TANAKA
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/786 , H01L29/00 , H01L29/785 , H01L29/78696
摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.
摘要翻译：实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

25. 发明申请

US20120273747A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120273747A1
公开(公告)日：2012-11-01
申请号：US13458042
申请日：2012-04-27
申请人： Masumi SAITOH , Toshinori NUMATA , Kiwamu SAKUMA , Haruka KUSAI , Takayuki ISHIKAWA
发明人： Masumi SAITOH , Toshinori NUMATA , Kiwamu SAKUMA , Haruka KUSAI , Takayuki ISHIKAWA
IPC分类号： H01L27/26 , H01L21/8239 , H01L27/088
CPC分类号： H01L21/823431 , H01L27/101 , H01L27/1211 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.
摘要翻译：根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。

26. 发明申请

US20110303972A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110303972A1
公开(公告)日：2011-12-15
申请号：US13082103
申请日：2011-04-07
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

27. 发明申请

US20100213533A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20100213533A1
公开(公告)日：2010-08-26
申请号：US12773967
申请日：2010-05-05
申请人： Masumi SAITOH , Ken Uchida
发明人： Masumi SAITOH , Ken Uchida
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变，并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

28. 发明申请

US20100051906A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100051906A1
公开(公告)日：2010-03-04
申请号：US12549140
申请日：2009-08-27
申请人： Takashi Yamauchi , Yoshifumi Nishi , Hiroto Honda , Kei Masunishi , Shinji Murai , Masumi Saitoh
发明人： Takashi Yamauchi , Yoshifumi Nishi , Hiroto Honda , Kei Masunishi , Shinji Murai , Masumi Saitoh
IPC分类号： H01L31/0352
CPC分类号： H01L27/14645 , H01L27/14683 , H01L31/0352
摘要： A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.
摘要翻译：提供了用于校正输入信号并输出校正信号的半导体器件。半导体器件包括半导体层，形成在半导体层的一个表面上并用作输入信号的输入端的多个第一导体，第二导体的数量大于第一导体的密度高于在半导体层的另一面形成的第一导体的第一导体的高杂质浓度区域设置在第二导体和半导体层之间的界面的半导体层侧，形成在另一面上的绝缘层，多个第三导体，形成在绝缘层上并用作用于输出处理信号的输出端。

29. 发明授权

US07605422B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07605422B2
公开(公告)日：2009-10-20
申请号：US11846830
申请日：2007-08-29
申请人： Masumi Saitoh , Ken Uchida
发明人： Masumi Saitoh , Ken Uchida
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L21/845 , H01L27/115 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.
摘要翻译：公开了一种半导体器件，其能够通过实现大的阈值电压偏移和长的保持时间来实现低电压驱动性和大的存储容量（小型化），同时抑制存储器单元之间的特性变化。该器件包括半导体存储单元，其具有形成在半导体衬底中的沟道区，沟道区上的隧道绝缘膜，隧道绝缘膜上的电荷存储绝缘膜，电荷存储膜上的控制电介质膜，控制电极在控制电介质膜上，以及在沟道区的相对端处的源/漏区。存储单元的沟道区域具有与沿着沟道长度的方向成直角的横截面，其宽度W和高度H都小于或等于10nm。

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