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21. 发明授权

US5604417A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5604417A
公开(公告)日：1997-02-18
申请号：US992448
申请日：1992-12-17
申请人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
发明人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
IPC分类号： H01L27/06 , H03K19/013 , H03R19/013
CPC分类号： H01L27/0623 , H03K19/0136
摘要： The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.
摘要翻译：该装置在单个基板上具有多个内部电路，用于接收外部输入信号并将其输出到内部电路的多个输入电路，以及用于接收从内部电路输出并从外部输出信号的多个输出电路，其中至少一个电路包括位于电源端侧的第一NPN双极晶体管的图腾柱输出级和位于地侧的第二NPN双极晶体管; 用于向第一NPN晶体管的基极提供脉冲作用的第一微分电路; 一对用于可控地驱动第二NPN晶体管的串联PMOS晶体管; 以及用于加速输出级晶体管关断的反馈MOS晶体管。电路可以用第二微分电路代替串联连接的一对PMOS晶体管。还可以实现电路的布置，其中图腾柱连接由PNP晶体管，电源端侧和地面或下拉侧的NPN或NMOS晶体管构成。利用这种电路配置，输出信号摆幅最大化，微分电路提供临时饱和以及快速恢复，从而减少传输延迟时间并实现低功耗。该设备可以由采用自举效应以及IIL（I2L）设计方案的电路来实现。

22. 发明授权

US5371023A Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor 失效
标题翻译：门电路，半导体集成电路器件及其制造方法，半导体存储器和微处理器
公开(公告)号：US5371023A
公开(公告)日：1994-12-06
申请号：US895815
申请日：1992-06-09
申请人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
发明人： Masataka Minami , Mitsuru Hiraki , Kazuo Yano , Atsuo Watanabe , Kouichi Seki , Takahiro Nagano , Kazushige Sato , Keiichi Yoshizumi , Ryuichi Izawa
IPC分类号： H01L27/06 , H01L27/105 , H01L21/20
CPC分类号： H01L27/105 , H01L27/0623
摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.
摘要翻译：公开了一种新颖的门电路。第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

23. 发明授权

US5144394A Semiconductor device and method for fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5144394A
公开(公告)日：1992-09-01
申请号：US575581
申请日：1990-08-31
申请人： Mitsuru Hirao , Masataka Minami , Shoji Shukuri
发明人： Mitsuru Hirao , Masataka Minami , Shoji Shukuri
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/8249 , H01L27/06 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66606 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/66545
摘要： The structure of a MOSFET and a method for fabricating the same is disclosed, with which it is possible to increase the driving capacity. Heretofore there was a problem that no measures were taken against the decrease in the channel width due to bird's beaks produced at the formation of a field oxide film and that the channel width at the completion of the manufacturing process was smaller than that foreseen during the design of the device. To overcome this problem, a MOSFET is provided in which the junction of the source or the drain is extended up to the end portions in the channel direction so that the effective channel width is determined by the width of the junction on the sides, where the junction is not extended up to the end portions in the channel direction.
摘要翻译：公开了一种MOSFET的结构及其制造方法，能够提高驱动能力。迄今为止，没有采取措施来防止在形成场氧化膜时产生的鸟喙导致的通道宽度的减小，并且制造过程完成时的通道宽度小于设计期间预期的通道宽度的设备。为了克服这个问题，提供了一种MOSFET，其中源极或漏极的连接在沟道方向上延伸到端部，使得有效沟道宽度由侧面上的结的宽度确定，其中接头不延伸到通道方向上的端部。

24. 发明授权

US4916500A MOS field effect transistor device with buried channel 失效
标题翻译： MOS场效应晶体管器件具有埋入通道
公开(公告)号：US4916500A
公开(公告)日：1990-04-10
申请号：US78987
申请日：1987-07-29
申请人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
发明人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
IPC分类号： H01L29/10 , H01L29/78 , H01L29/786 , H01L29/808
CPC分类号： H01L29/78696 , H01L29/105 , H01L29/78 , H01L29/7838 , H01L29/808
摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.
摘要翻译：本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底导电类型或所述绝缘体。

25. 发明授权

US08482083B2 Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
标题翻译：半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元
公开(公告)号：US08482083B2
公开(公告)日：2013-07-09
申请号：US12821329
申请日：2010-06-23
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致出现微图案化困难的问题。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

26. 发明申请

US20130077791A1 REVOCATION LIST GENERATION DEVICE, REVOCATION LIST GENERATION METHOD, AND CONTENT MANAGEMENT SYSTEM 有权
标题翻译：撤销清单生成装置，撤销清单生成方法和内容管理系统
公开(公告)号：US20130077791A1
公开(公告)日：2013-03-28
申请号：US13702137
申请日：2012-04-17
申请人： Masayuki Kozuka , Takahiro Yamaguchi , Toshihisa Nakano , Kaoru Murase , Motoji Ohmori , Makoto Morise , Masataka Minami
发明人： Masayuki Kozuka , Takahiro Yamaguchi , Toshihisa Nakano , Kaoru Murase , Motoji Ohmori , Makoto Morise , Masataka Minami
IPC分类号： H04L9/08
CPC分类号： H04L9/0891 , H04L9/3268 , H04L63/062 , H04L2463/101
摘要： Provided is a revocation list generation device that can suppress an increase in the amount of data of a revocation list. A revocation list generation device 500g that generates a revocation list includes an acquisition unit 501g that acquires, for a content, a revocation identifier identifying a revoked public key certificate allocated to an apparatus related to use of the content, a revocation list generation unit 502g that generates a revocation list including the acquired revocation identifier associated with the content, and an output unit 503g that outputs the revocation list.
摘要翻译：提供了可以抑制撤销列表的数据量的增加的撤销列表生成装置。生成撤销列表的撤销列表生成装置500g包括获取单元501g，对于内容，获取识别分配给与使用该内容有关的装置的撤销公钥证书的撤销标识符，撤销列表生成部502g，生成包括与内容相关联的获取的吊销标识符的撤销列表，以及输出撤销列表的输出单元503g。

27. 发明申请

US20130049131A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130049131A1
公开(公告)日：2013-02-28
申请号：US13616435
申请日：2012-09-14
申请人： Kenichi OSADA , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi OSADA , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L27/092
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区域的衬底电接触，这将导致不对称性的降低导致微图案化困难。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

28. 发明申请

US20130001772A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130001772A1
公开(公告)日：2013-01-03
申请号：US13607766
申请日：2012-09-09
申请人： Yuki KOIDE , Masataka MINAMI
发明人： Yuki KOIDE , Masataka MINAMI
IPC分类号： H01L23/498
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

29. 发明申请

US20120311446A1 CONTENT RECORDING DEVICE, CONTENT RECORDING METHOD, CONTENT RECORDING PROGRAM, RECORDING MEDIUM, INTEGRATED CIRCUIT AND CONTENT RECORDING AND REPRODUCTION SYSTEM 审中-公开
标题翻译：内容记录装置，内容记录方法，内容记录程序，记录介质，集成电路和内容记录和再现系统
公开(公告)号：US20120311446A1
公开(公告)日：2012-12-06
申请号：US13578060
申请日：2011-04-08
申请人： Toshihisa Nakano , Masataka Minami , Masayuki Kozuka
发明人： Toshihisa Nakano , Masataka Minami , Masayuki Kozuka
IPC分类号： G06F3/048
CPC分类号： H04N9/8205 , G11B20/00086 , G11B20/0021 , G11B20/00746 , G11B20/00753 , G11B20/00789 , G11B20/0084 , G11B27/105 , G11B27/11 , G11B27/329 , G11B27/34 , G11B2220/2541
摘要： A content recording device includes: an input/output unit 201 that reads, from a first recording medium, content and default playback auxiliary information used to generate a default menu screen for playing back the content; a playback unit 203 that includes a first display mechanism for generating the default menu screen by using the default playback auxiliary information and displaying the generated default menu screen; a transmission/reception unit 208 that acquires, from outside, additional playback auxiliary information used to generate an additional menu screen different from the default menu screen and displayable by a second display mechanism; and a storage unit 202 that writes the content and the default playback auxiliary information into a second recording medium and further writes, via the input/output unit 201, the additional playback auxiliary information into a predetermined reading location from which a playback device including the second display mechanism reads the additional playback auxiliary information.
摘要翻译：内容记录装置包括：输入/输出单元201，其从第一记录介质读取用于生成用于回放内容的默认菜单屏幕的内容和默认播放辅助信息; 播放单元203，其包括通过使用默认播放辅助信息生成默认菜单屏幕并显示所生成的默认菜单屏幕的第一显示机构; 从外部获取用于生成与默认菜单画面不同的可由第二显示机构显示的附加菜单画面的附加重放辅助信息的发送/接收单元208; 以及存储单元202，其将内容和默认回放辅助信息写入第二记录介质，并且还经由输入/输出单元201将附加回放辅助信息写入到预定的读取位置，从该位置开始包括第二记录介质显示机构读取附加播放辅助信息。

30. 发明申请

US20120189281A1 PLAYBACK DEVICE, CONTENT DISTRIBUTION SYSTEM, PLAYBACK METHOD, COMPUTER PROGRAM AND INTEGRATED CIRCUIT 有权
标题翻译：回放设备，内容分发系统，回放方法，计算机程序和集成电路
公开(公告)号：US20120189281A1
公开(公告)日：2012-07-26
申请号：US13496956
申请日：2011-03-24
申请人： Toshihisa Nakano , Masataka Minami , Masayuki Kozuka
发明人： Toshihisa Nakano , Masataka Minami , Masayuki Kozuka
IPC分类号： H04N5/91
CPC分类号： H04N21/4325 , G06F21/10 , G11B20/00224 , G11B20/0071 , G11B20/00869 , G11B2220/61 , H04N21/2541 , H04N21/2662 , H04N21/4182 , H04N21/4184 , H04N21/4627 , H04N21/63775 , H04N21/6582
摘要： To provide a playback device capable of requesting for a content generated in a format compatible with its processing capability and playing back the content, with no need of user input of a user ID or the like. A playback device for playing back contents reads, from an external recording medium, a playback right of a content to play back one or more contents that each have been generated based on a content and in a format compatible with a processing capability different for each playback device, and transmits the playback right and capability information indicating a processing capability of the playback device to a server device. The playback device acquires, from the server device, one of the one or more contents corresponding to the playback right in a format compatible with its processing capability indicated by the capability information, and plays back the acquired content.
摘要翻译：为了提供能够请求与其处理能力兼容的格式生成的内容并且播放内容的播放设备，而不需要用户输入用户ID等。用于回放内容的回放设备从外部记录介质读取内容的播放权，以基于内容播放每个已经生成的一个或多个内容，并以与每个播放不同的处理能力兼容的格式将播放权和表示播放装置的处理能力的能力信息发送到服务器装置。播放装置从服务器装置以与能力信息所表示的处理能力相兼容的格式获取对应于回放权的一个或多个内容中的一个，并且回放所获取的内容。

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