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21. 发明授权

US06677230B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06677230B2
公开(公告)日：2004-01-13
申请号：US10197411
申请日：2002-07-18
申请人： Natsuki Yokoyama , Masakazu Kawano
发明人： Natsuki Yokoyama , Masakazu Kawano
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , H01L21/28556 , H01L21/76877
摘要： A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (“through holes or local interconnection holes”) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.
摘要翻译：包含第二金属硅化物作为主要构成元素的层或包含第二金属作为主要构成元素的层通过一个单一化学气相沉积工艺同时形成到蚀刻在电介质中的两组开口的底表面薄膜在基材上。包含硅作为主要构成元件的表面在第一组开口的每个底部（“通孔或局部互连孔”）处露出，包括作为主要构成元件的第一金属硅化物的表面在第二组开口，并且包括第一金属作为主要构成元件的表面暴露在第三组开口的每个底部。该制造方法即使蚀刻的开口区域具有不同的深度，形状或尺寸，也提供了与插头或局部互连相关联的来自扩散层的低接触电阻和足够小的结漏电流。

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