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21. 发明授权

US07240187B2 Method and apparatus to support legacy master boot record (MBR) partitions 失效
标题翻译：支持传统主引导记录（MBR）分区的方法和设备
公开(公告)号：US07240187B2
公开(公告)日：2007-07-03
申请号：US10935956
申请日：2004-09-08
申请人： Mahesh S. Natu
发明人： Mahesh S. Natu
IPC分类号： G06F9/00 , G06F15/177 , G06F13/00
CPC分类号： G06F9/4411 , G06F9/4406
摘要： Disclosed is a method, apparatus, and system in which a basic input/output BIOS is run and a non-volatile memory coupled to the BIOS is read. The BIOS determines if legacy partition address data is not present for a disk partition identified in the non-volatile memory, and if legacy partition address data is not present for the disk partition, legacy partition address data may be obtained by a legacy OPROM. The disk drive may then be updated with the legacy partition address data.
摘要翻译：公开了一种方法，装置和系统，其中运行基本输入/输出BIOS并且读取耦合到BIOS的非易失性存储器。 BIOS确定对于在非易失性存储器中标识的磁盘分区是否不存在传统分区地址数据，并且如果传统分区地址数据不存在于磁盘分区，则传统分区地址数据可以由传统OPROM获得。然后可以用传统分区地址数据来更新磁盘驱动器。

22. 发明授权

US07117353B2 Methods and apparatus to enable console redirection in a multiple execution environment 有权
标题翻译：在多个执行环境中启用控制台重定向的方法和设备
公开(公告)号：US07117353B2
公开(公告)日：2006-10-03
申请号：US10654847
申请日：2003-09-04
申请人： Mahesh S. Natu , Rahul Khanna
发明人： Mahesh S. Natu , Rahul Khanna
IPC分类号： G06F9/00
CPC分类号： G06F3/1454 , G06F9/45512
摘要： Methods and apparatus to enable console redirection in a multiple execution environment are disclosed. In an example method, at least one periodic interrupt in a first basic input/output system (BIOS) execution environment of a local console is initiated. Data associated with a second BIOS execution environment of the local console is retrieved. The data associated with the second BIOS execution environment is communicated to a remote terminal.
摘要翻译：公开了在多个执行环境中启用控制台重定向的方法和装置。在示例性方法中，启动本地控制台的第一基本输入/输出系统（BIOS）执行环境中的至少一个周期性中断。检索与本地控制台的第二BIOS执行环境相关联的数据。与第二BIOS执行环境相关联的数据被传送到远程终端。

23. 发明授权

US06910113B2 Executing large device firmware programs 有权
标题翻译：执行大型设备固件程序
公开(公告)号：US06910113B2
公开(公告)日：2005-06-21
申请号：US09948805
申请日：2001-09-07
申请人： Mahesh S. Natu
发明人： Mahesh S. Natu
IPC分类号： G06F9/445 , G06F12/06 , G06F12/00
CPC分类号： G06F8/60 , G06F12/0623
摘要： A processor-based system includes a system firmware program (e.g., the system basic input/output system (BIOS)) to execute a device firmware program (e.g., a device driver) stored on a storage device (e.g., an expansion read-only-memory (ROM)). For execution, the processor-based system uses a system memory including a designated region intended for storing the device firmware program. The system firmware program determines whether the device firmware program exceeds the capacity of the designated region. And, if so, the system firmware program stores the device firmware program in the designated region and at least one another location in the system memory thus supporting larger expansion ROMs on some platforms.
摘要翻译：基于处理器的系统包括用于执行存储在存储设备上的设备固件程序（例如，设备驱动程序）的系统固件程序（例如，系统基本输入/输出系统（BIOS））（例如扩展只读 - 内存（ROM））。为了执行，基于处理器的系统使用包括用于存储设备固件程序的指定区域的系统存储器。系统固件程序确定设备固件程序是否超过指定区域的容量。而且，如果是这样，系统固件程序将设备固件程序存储在系统存储器中的指定区域和至少另一个位置，从而在某些平台上支持更大的扩展ROM。

24. 发明申请

US20160232103A1 BLOCK STORAGE APERTURES TO PERSISTENT MEMORY 审中-公开
标题翻译：对存储记忆体的存储存储空间
公开(公告)号：US20160232103A1
公开(公告)日：2016-08-11
申请号：US14127553
申请日：2013-09-26
申请人： Mark A. Schmisseur , Andy M. Rudoff , Murugasamy Nachimuthu , Mahesh S. Natu , Richard P. Mangold , Douglas D. Stewart
发明人： Mark A. Schmisseur , Andy M. Rudoff , Murugasamy Nachimuthu , Mahesh S. Natu , Richard P. Mangold , Douglas D. Stewart
IPC分类号： G06F12/10 , G06F11/07 , G06F13/16 , G06F12/14 , G06F3/06
CPC分类号： G06F12/10 , G06F3/061 , G06F3/0622 , G06F3/0659 , G06F3/0679 , G06F11/073 , G06F11/0772 , G06F12/0246 , G06F12/1408 , G06F12/1441 , G06F13/1668 , G06F2212/1052 , G06F2212/202 , G06F2212/2022 , G06F2212/402 , G06F2212/7201
摘要： Apparatus and methods for accessing a non-volatile memory (NVM) device in a computer system that includes at least one host processor and at least one memory bus. The NVM device is communicably coupleable to the memory bus through an NVM device controller, thereby allowing the host processor to access persistent data storable within the NVM device by issuing one or more memory load/store commands to the NVM device controller over the memory bus. Because the NVM device controller includes at least one block window or aperture that defines at least one address range for accessing the persistent data storable within the NVM device, the computer system can exploit the full capacity of the NVM device without being unduly constrained by physical addressing limits imposed by the host processor, or by limits imposed by an operating system executed by the host processor.
摘要翻译：用于访问包括至少一个主处理器和至少一个存储器总线的计算机系统中的非易失性存储器（NVM）设备的装置和方法。 NVM设备通过NVM设备控制器可通信地耦合到存储器总线，从而允许主机处理器通过在存储器总线上向NVM设备控制器发出一个或多个存储器加载/存储命令来访问可存储在NVM设备内的持久数据。因为NVM设备控制器包括至少一个限定了至少一个地址范围的块窗口或孔径，用于访问可存储在NVM设备内的持久数据，所以计算机系统可以利用NVM设备的全部容量，而不会被物理寻址过度约束由主处理器施加的限制，或由主处理器执行的操作系统施加的限制。

25. 发明授权

US08812828B2 Methods and apparatuses for recovering usage of trusted platform module 有权
标题翻译：恢复信任平台模块使用的方法和装置
公开(公告)号：US08812828B2
公开(公告)日：2014-08-19
申请号：US12947218
申请日：2010-11-16
申请人： Shamanna M. Datta , Mahesh S. Natu
发明人： Shamanna M. Datta , Mahesh S. Natu
IPC分类号： G06F9/24 , G06F21/57 , G06F21/00 , G06F11/07
CPC分类号： G06F21/57 , G06F11/0793 , G06F21/00 , G06F21/575
摘要： Methods and systems to perform platform security in conjunction with hardware-base root of trust logic are presented. In one embodiment, a method includes determining whether a status from an authenticated code module is indicative of an error or not. The method further includes determining whether the hardware-based root of trust logic is enabled based on content in a non-volatile memory location. If the hardware-based root of trust is enabled and the status is indicative of an error, the method further includes writing to the non-volatile memory location to disable hardware-based root of trust logic during a next boot sequence. In one embodiment, a platform initializes and uses the trusted platform module in conjunction with the hardware-based root of trust logic or with a platform-based root of trust logic.
摘要翻译：提出了结合信任逻辑的硬件根本来执行平台安全性的方法和系统。在一个实施例中，一种方法包括确定来自认证代码模块的状态是否指示错误。该方法还包括基于非易失性存储器位置中的内容来确定信任逻辑的基于硬件的根是否被启用。如果启用了基于硬件的信任根，并且状态指示了错误，则该方法还包括在下一个引导序列期间写入非易失性存储器位置以禁用基于硬件的信任逻辑根。在一个实施例中，平台与基于硬件的信任逻辑根或基于平台的信任逻辑逻辑基础一起初始化并使用可信平台模块。

26. 发明授权

US08301907B2 Supporting advanced RAS features in a secured computing system 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US08301907B2
公开(公告)日：2012-10-30
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F11/30
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

27. 发明授权

US08146150B2 Security management in multi-node, multi-processor platforms 有权
标题翻译：多节点，多处理器平台的安全管理
公开(公告)号：US08146150B2
公开(公告)日：2012-03-27
申请号：US11968128
申请日：2007-12-31
申请人： Mahesh S. Natu , Sham Datta
发明人： Mahesh S. Natu , Sham Datta
IPC分类号： G06F7/04
CPC分类号： G06F21/85
摘要： Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.
摘要翻译：本节介绍了多节点和多处理器的安全管理。可以在多个节点中的任一个的TPM中确保数据，每个节点包括一个或多个处理器。可以使用硬件钩来保护安全数据，以防止未经授权的访问安全信息。可以通过要求VMM，OS，ACM或处理器硬件的许可来保护安全层级以保护某些存储器地址免受访问。可以将安全数据的存在传送到每个节点以确保数据被保护。描述其他实施例。

28. 发明申请

US20110154006A1 MECHANISM FOR DETECTING A NO-PROCESSOR SWAP CONDITION AND MODIFICATION OF HIGH SPEED BUS CALIBRATION DURING BOOT 有权
标题翻译：检测无处理器交换条件的机制和引导期间高速公交校准的修改
公开(公告)号：US20110154006A1
公开(公告)日：2011-06-23
申请号：US12643108
申请日：2009-12-21
申请人： MAHESH S. NATU , John V. Lovelace , Rajesh P. Banginwar
发明人： MAHESH S. NATU , John V. Lovelace , Rajesh P. Banginwar
IPC分类号： G06F9/00
CPC分类号： G06F21/74 , G06F9/4403 , G06F21/44 , G06F21/575 , G06F21/71 , G06F21/73 , G06F21/85 , G06F2221/2105 , G06F2221/2129 , G06F2221/2149 , G06F2221/2153
摘要： Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.
摘要翻译：存储器通道训练参数是存储器件，处理器和存储器通道的电特性的函数。如果BIOS可以确定自上次启动以来，内存设备，主板和处理器没有更改，则可跳过培训步骤。存储器件包含用于跟踪目的的序列号，并且大多数主板都包含序列号。许多处理器不提供BIOS可以跟踪处理器的机制。这里描述的是允许BIOS跟踪处理器并检测交换而不违反隐私/安全要求的技术。

29. 发明申请

US20090089566A1 SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US20090089566A1
公开(公告)日：2009-04-02
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

30. 发明授权

US07203767B2 System processing data packets received from remote host to control system operation according to adjustable timer interrupts based on data flow rate 有权
标题翻译：系统处理从远程主机收到的数据包，根据数据流速可调节定时器中断来控制系统运行
公开(公告)号：US07203767B2
公开(公告)日：2007-04-10
申请号：US11351991
申请日：2006-02-09
申请人： Rahul Khanna , Mahesh S. Natu
发明人： Rahul Khanna , Mahesh S. Natu
IPC分类号： G06F15/16
CPC分类号： G06F9/4411 , G06F9/4812 , G06F9/4825 , G06F9/544 , H04L67/38 , H04L69/12 , H04L69/28
摘要： A technique for providing communication between two computers through a network in a way to allow one computer to control the other.
摘要翻译：一种用于通过网络在两台计算机之间提供通信的技术，以允许一台计算机控制另一台计算机。

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