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21. 发明授权

US08604536B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604536B2
公开(公告)日：2013-12-10
申请号：US12406841
申请日：2009-03-18
申请人： Katsuyuki Sekine , Yoshio Ozawa
发明人： Katsuyuki Sekine , Yoshio Ozawa
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/66833
摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
摘要翻译：半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

22. 发明申请

US20130228737A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130228737A1
公开(公告)日：2013-09-05
申请号：US13601494
申请日：2012-08-31
申请人： Hiroyuki FUKUMIZU , Yasuhiro Nojiri , Katsuyuki Sekine
发明人： Hiroyuki FUKUMIZU , Yasuhiro Nojiri , Katsuyuki Sekine
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： According to an embodiment, a nonvolatile semiconductor memory device comprises memory cells in each of which are series-connected: a variable resistance element including a metal oxide; an electrode including a polysilicon layer and a SiGe layer formed between the polysilicon layer and the metal oxide; and a bipolar type current rectifying element.
摘要翻译：根据实施例，非易失性半导体存储器件包括：串联连接的存储单元，包括金属氧化物的可变电阻元件; 在所述多晶硅层和所述金属氧化物之间形成包括多晶硅层和SiGe层的电极; 和双极型电流整流元件。

23. 发明申请

US20120217461A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120217461A1
公开(公告)日：2012-08-30
申请号：US13404795
申请日：2012-02-24
申请人： Shigeki KOBAYASHI , Takashi Shigeoka , Mitsuru Sato , Takahiro Hirai , Katsuyuki Sekine , Kazuya Kinoshita , Soichi Yamazaki , Ryota Fujitsuka , Kensuke Takahashi , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
发明人： Shigeki KOBAYASHI , Takashi Shigeoka , Mitsuru Sato , Takahiro Hirai , Katsuyuki Sekine , Kazuya Kinoshita , Soichi Yamazaki , Ryota Fujitsuka , Kensuke Takahashi , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L45/00 , H01L21/8239 , B82Y99/00
CPC分类号： H01L27/2409 , B82Y10/00 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.
摘要翻译：根据实施例的半导体存储器件包括：设置在基板上的第一线; 设置在第一线和基板之间以与第一线相交的第二线; 以及包括第一存储单元的第一存储单元阵列，每个第一存储单元设置在第一行和第二行的相应交点处，并且包括串联连接的电流整流元件和可变电阻器。第一存储单元的可变电阻器包括第一记录层和第二记录层，第一记录层由第一金属材料的氧化物制成，第二记录层由第一金属材料制成并形成为与第一记录层接触。第二记录层比第一记录层更靠近第一行。

24. 发明授权

US07999304B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07999304B2
公开(公告)日：2011-08-16
申请号：US12026942
申请日：2008-02-06
申请人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
发明人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/512 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.
摘要翻译：半导体器件包括半导体衬底和非易失性存储单元，每个单元包括具有沟道长度和沟道宽度的沟道区，隧道绝缘膜，浮栅电极，控制栅电极，电极间绝缘在浮置控制栅电极和控制栅极电极的侧壁表面之间的电极侧壁绝缘膜，电极侧壁绝缘膜包括具有第一和第二介电常数的第一和第二绝缘膜，所述第一介电常数高于所述第二介电常数，所述第二介电常数高于氮化硅膜的介电常数，所述第一绝缘膜位于所述浮动栅极和控制栅电极之间的面对区域的中心区域中，第二绝缘区域位于面对区域的两端区域中并从两端口突出 ons。

25. 发明申请

US20110175048A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110175048A1
公开(公告)日：2011-07-21
申请号：US13004287
申请日：2011-01-11
申请人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1273 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.
摘要翻译：根据一个实施例，非易失性存储器件包括第一和第二导电层，电阻变化层和整流元件。第一导电层具有第一和第二主表面。第二导电层具有第三和第四主表面，侧面和拐角部分。第三主表面面向第一主表面并且包括平行于第一主面的平面，并且设置在第四主表面和第一主表面之间。角部设置在第三主表面和侧面之间。角部具有高于第三主表面的曲率。电阻变化层设置在第一和第二导电层之间。整流元件面向第一导电层的第二主表面。第三主表面的面积小于第二主表面的面积。

26. 发明申请

US20110069530A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110069530A1
公开(公告)日：2011-03-24
申请号：US12823467
申请日：2010-06-25
申请人： Katsuyuki SEKINE , Ryota Fujitsuka , Yoshio Ozawa
发明人： Katsuyuki SEKINE , Ryota Fujitsuka , Yoshio Ozawa
IPC分类号： G11C11/00 , H01L21/66
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/101
摘要： According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.
摘要翻译：根据一个实施例，提供了一种制造非易失性存储器件的方法。在该方法中，可以将第一电压施加到具有电阻可变的电阻值的高电阻和低电阻的可变电阻元件。在该方法中，在施加了第一电压的可变电阻元件的电阻值大于低电阻的电阻值的情况下，可以向可变电阻元件施加第二电压，并且不大于电阻值为高电阻。此外，在该方法中，可以重复向可变电阻元件施加第二电压，直到施加了第二电压的可变电阻元件的电阻值落在低电阻的电阻值的范围内。

27. 发明授权

US07863166B2 Method of manufacturing semiconductor storage device 有权
标题翻译：制造半导体存储装置的方法
公开(公告)号：US07863166B2
公开(公告)日：2011-01-04
申请号：US12646563
申请日：2009-12-23
申请人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
发明人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76264 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203 , H01L29/66825
摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
摘要翻译：一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在开口部。然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。然后，在硅单晶层上形成存储单元阵列。

28. 发明申请

US20100314602A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100314602A1
公开(公告)日：2010-12-16
申请号：US12728579
申请日：2010-03-22
申请人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
发明人： Kensuke Takano , Yoshio Ozawa , Katsuyuki Sekine , Junichi Wada
IPC分类号： H01L45/00 , H01L21/28
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1666
摘要： A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
摘要翻译：非易失性存储器件包括：第一导电层; 第二导电层; 第一电阻变化层，设置在所述第一导电层和所述第二导电层之间，并且具有通过施加电场和通过电流中的至少一个而改变的电阻; 以及第一侧面层，设置在第一电阻变化层的侧面上，其氧浓度高于第一电阻变化层中的氧浓度

29. 发明申请

US20100237402A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有三维方向记忆细胞的半导体存储器件及其制造方法
公开(公告)号：US20100237402A1
公开(公告)日：2010-09-23
申请号：US12726952
申请日：2010-03-18
申请人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
摘要翻译：第一选择晶体管形成在半导体衬底上。存储单元晶体管堆叠在第一选择晶体管上并串联连接。在存储单元晶体管上形成第二选择晶体管。存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜该块介质膜并用作栅电极。

30. 发明申请

US20100190317A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SILICON OXIDE FILM FORMING METHOD 有权
标题翻译：半导体器件制造方法和氧化硅膜形成方法
公开(公告)号：US20100190317A1
公开(公告)日：2010-07-29
申请号：US12691483
申请日：2010-01-21
申请人： Kazuaki IWASAWA , Takeshi Hoshi , Keisuke Nakazawa , Shogo Matsuo , Takashi Nakao , Ryu Kato , Tetsuya Kai , Katsuyuki Sekine
发明人： Kazuaki IWASAWA , Takeshi Hoshi , Keisuke Nakazawa , Shogo Matsuo , Takashi Nakao , Ryu Kato , Tetsuya Kai , Katsuyuki Sekine
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
摘要翻译：半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理温度以在元件隔离槽内形成被覆氧化硅膜。

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