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21. 发明申请

US20100034031A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100034031A1
公开(公告)日：2010-02-11
申请号：US12461277
申请日：2009-08-06
申请人： Sang-Seok Kang , Hyung-Dong Kim
发明人： Sang-Seok Kang , Hyung-Dong Kim
IPC分类号： G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/406 , G11C5/147 , G11C11/40615 , G11C11/4074 , G11C2211/4068
摘要： A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.
摘要翻译：半导体存储器件包括：电压电平选择单元，被配置为响应于自刷新命令信号，根据熔丝程序输出多个电压电平选择信号;以及参考电压发生器，被配置为接收参考电压并输出目标参考响应于电压电平选择信号，具有取决于正常模式或自刷新模式的不同电压电平的电压。

22. 发明申请

US20060290414A1 Charge pump circuit and semiconductor memory device having the same 审中-公开
标题翻译：电荷泵电路和具有该电荷泵电路的半导体存储器件
公开(公告)号：US20060290414A1
公开(公告)日：2006-12-28
申请号：US11435336
申请日：2006-05-16
申请人： Jung-Sik Kim , Hyung-Dong Kim
发明人： Jung-Sik Kim , Hyung-Dong Kim
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump circuit includes a switch for transmitting an electric charge between a pumping node and an output of the charge pump circuit such that a pre-charge voltage level is applied to a control node during pre-charge operation and a pumping control voltage level is applied to the control node during pumping operation, and a control circuit for changing a level of the control node in response to a control signal to turn off the switch.
摘要翻译：电荷泵电路包括用于在泵送节点和电荷泵电路的输出之间传送电荷的开关，使得在预充电操作期间将预充电电压电压施加到控制节点，并且泵控制电压电平为在泵送操作期间施加到控制节点，以及控制电路，用于响应于控制信号改变控制节点的电平以关闭开关。

23. 发明申请

US20060114731A1 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US20060114731A1
公开(公告)日：2006-06-01
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

24. 发明授权

US06707738B2 Semiconductor memory device having mesh-type structure of precharge voltage line 有权
标题翻译：具有预充电电压线的网状结构的半导体存储器件
公开(公告)号：US06707738B2
公开(公告)日：2004-03-16
申请号：US10145001
申请日：2002-05-14
申请人： Jang-Seok Choi , Sung-min Yim , Hyung-dong Kim , Duk-ha Park
发明人： Jang-Seok Choi , Sung-min Yim , Hyung-dong Kim , Duk-ha Park
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays. During a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second precharge voltage line, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.
摘要翻译：提供具有预充电电压线的网状结构的半导体存储器件。半导体存储器件包括多个存储单元阵列，多个位线预充电电路单元，以及第一预充电电压线和第二预充电电压线。多个存储单元阵列中的每一个包括多个存储单元和多个位线对，用于向每个存储单元输出数据和从每个存储单元接收数据，并且以矩阵形式布置。多个位线预充电电路单元将存储单元阵列的相应位线对预充电并将其均衡为预定的预充电电压。第一预充电电压线和第二预充电电压线在多个存储单元阵列之间的每个区域中以网格布置。在第一操作模式下，第一预充电电压线和第二预充电电压线提供公共预充电电压，并且在第二预充电电压线期间，具有不同电平的预充电电压在第一和第二预充电电压线处被提供给预充电存储器具有不同预充电电压的彼此相邻的单元。

25. 发明授权

US5640360A Address buffer of semiconductor memory device 失效
标题翻译：半导体存储器件的地址缓冲器
公开(公告)号：US5640360A
公开(公告)日：1997-06-17
申请号：US591118
申请日：1996-01-25
申请人： Gyu-Hong Kim , Jin-Man Han , Hyung-Dong Kim
发明人： Gyu-Hong Kim , Jin-Man Han , Hyung-Dong Kim
IPC分类号： G11C11/413 , G06F12/02 , G11C11/408 , B11C8/00
CPC分类号： G11C11/4082
摘要： An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.
摘要翻译：用于半导体存储器件的地址缓冲电路包括分别根据第一和第二地址输入控制信号可选择地连接到第一节点的第一和第二地址输入。该装置还包括由刷新模式信号控制并选择性地输出第一或第二地址使能信号的第一和第二开关。此外，提供锁存器，其将输入到第一节点的地址信号锁存，并且在所选择的第一或第二地址使能信号的周期中输出锁存的地址信号。

26. 发明申请

US20080211542A1 Input buffer with wide input voltage range 审中-公开
标题翻译：输入缓冲器，输入电压范围宽
公开(公告)号：US20080211542A1
公开(公告)日：2008-09-04
申请号：US12076312
申请日：2008-03-17
申请人： Dong-il Seo , Hyung-dong Kim , Jung-sik Kim
发明人： Dong-il Seo , Hyung-dong Kim , Jung-sik Kim
IPC分类号： H03K19/0185
CPC分类号： H03K19/018528
摘要： The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.
摘要翻译：输入缓冲器由数据输入/输出电源电压驱动。输入缓冲器从数据输入/输出电源电压和数据输入/输出接地电压之间摆动的输入信号产生输出信号。

27. 发明授权

US07173872B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07173872B2
公开(公告)日：2007-02-06
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

28. 发明授权

US07016248B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07016248B2
公开(公告)日：2006-03-21
申请号：US10423505
申请日：2003-04-25
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号（例如，晶片烧入测试模式）使得高电压发生器能够使能的使能信号。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

29. 发明授权

US5886933A Boost voltage generator for controlling a memory cell array 失效
标题翻译：升压电压发生器，用于控制存储单元阵列
公开(公告)号：US5886933A
公开(公告)日：1999-03-23
申请号：US879757
申请日：1997-06-19
申请人： Dong-il Seo , Hyung-dong Kim
发明人： Dong-il Seo , Hyung-dong Kim
IPC分类号： G11C11/413 , G11C5/14 , G11C8/08 , G11C11/407 , G11C7/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A boost voltage generating circuit for a memory device prevents excessive voltage on a word line for a memory cell array and reduces power consumption by utilizing an internal array reference voltage signal as a reference signal for the boost voltage generating circuit. The circuit maintains the boost voltage power supply signal at a predetermined level independently of the voltage level of an internal peripheral reference voltage signal which is applied to a peripheral circuit and which can be increased to increase the speed of the memory device without causing excessive voltage on the word line. The boost voltage generating circuit includes a level detector circuit which receives the array reference voltage signal as a reference signal. The boost voltage generating circuit also includes a pulse generator and a pumping circuit which utilize the array reference voltage signal as a power supply.
摘要翻译：用于存储器件的升压电压产生电路防止用于存储单元阵列的字线上的过高电压，并且通过利用内部阵列参考电压信号作为升压电压产生电路的参考信号来降低功耗。该电路将升压电压电源信号保持在预定电平，独立于施加到外围电路的内部周边参考电压信号的电压电平，并且可以增加以提高存储器件的速度，而不会导致过高的电压字线。升压电压产生电路包括电平检测器电路，其接收阵列参考电压信号作为参考信号。升压电压产生电路还包括利用阵列参考电压信号作为电源的脉冲发生器和泵浦电路。

30. 发明授权

US07922368B2 Light module and flat light unit in a liquid crystal display device 有权
标题翻译：光模块和平板灯装置在液晶显示装置中
公开(公告)号：US07922368B2
公开(公告)日：2011-04-12
申请号：US11955029
申请日：2007-12-12
申请人： Jae Bum Kim , Jae Kyung Kang , Sung Keun Lee , Jae Jin Kim , Hyung Dong Kim , Sang Dae Lee
发明人： Jae Bum Kim , Jae Kyung Kang , Sung Keun Lee , Jae Jin Kim , Hyung Dong Kim , Sang Dae Lee
IPC分类号： F21V7/00
CPC分类号： G02B19/0066 , G02B19/0014 , G02B27/0955 , G02F1/133603
摘要： A liquid crystal display device may include a backlight unit for providing light for the display. A backlight unit may include light modules. The light modules include colored LEDs surrounded by a first lens for refracting the light from the LEDs. A second lens surrounds the first lens for further refraction of the light to improve brightness and the uniformity of the light.
摘要翻译：液晶显示装置可以包括用于为显示器提供光的背光单元。背光单元可以包括光模块。光模块包括被第一透镜包围的彩色LED，以折射来自LED的光。第二透镜围绕第一透镜以进一步折射光以改善光的亮度和均匀性。

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