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21. 发明授权

US07773953B2 Wireless transceiving apparatus for variability of signal processing band 有权
标题翻译：用于信号处理频带变化的无线收发装置
公开(公告)号：US07773953B2
公开(公告)日：2010-08-10
申请号：US11224811
申请日：2005-09-12
申请人： Seon-Ho Han , Mun-Yang Park , Hyun-Kyu Yu , Cheon-Soo Kim
发明人： Seon-Ho Han , Mun-Yang Park , Hyun-Kyu Yu , Cheon-Soo Kim
IPC分类号： H04B1/40
CPC分类号： H04B1/405
摘要： Provided is a wireless transceiving apparatus for variability of signal processing band, in which at least one resonator of an analog processor and a VCO are simultaneously controlled using a frequency synthesizer, and a frequency of the VCO and a resonance frequency of the analog processor are controlled to have a rational number ratio, thereby capable of varying the signal processing band. The wireless transceiving apparatus includes: an analog processor having a plurality of resonators on a path of transmission/reception signals, for performing analog signal processing; a digital processor for performing digital signal processing on an output signal of the analog processor or data to be transmitted to the analog processor; and a frequency synthesizer for providing a local oscillation (LO) frequency and a controlling signal to the resonators of the analog processor so as to vary a signal processing band of the analog processor.
摘要翻译：提供了一种用于信号处理频带的可变性的无线收发装置，其中使用频率合成器同时控制模拟处理器和VCO的至少一个谐振器，并且控制VCO的频率和模拟处理器的谐振频率具有有理数比，由此能够改变信号处理频带。无线收发装置包括：模拟处理器，在发送/接收信号的路径上具有多个谐振器，用于执行模拟信号处理; 用于对模拟处理器的输出信号执行数字信号处理的数字处理器或将被发送到模拟处理器的数据; 以及用于向模拟处理器的谐振器提供本地振荡（LO）频率和控制信号以便改变模拟处理器的信号处理频带的频率合成器。

22. 发明申请

US20100134334A1 METHOD AND DEVICE FOR DIGITALLY CORRECTING DC OFFSET 有权
标题翻译：用于数字校正直流偏置的方法和装置
公开(公告)号：US20100134334A1
公开(公告)日：2010-06-03
申请号：US12628186
申请日：2009-11-30
申请人： Jae Hoon SHIM , Hyun Kyu Yu
发明人： Jae Hoon SHIM , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： H03F3/005
摘要： There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator.
摘要翻译：提供了数字直流（DC）偏移校正方法和装置。该装置包括数模转换器，根据输入代码值对负载电容器充电并产生负载电容器的初始电压值; 当离散时间放大器和滤波器和负载电容器彼此连接时，比较器将基于初始电压值的离散时间放大器和滤波器的输出DC偏移值与预设输出DC偏移值进行比较; 以及根据比较器的比较结果改变数模转换器的输入代码值的控制器。

23. 发明授权

US07643598B2 Frequency lock detector 有权
标题翻译：频率锁定检测器
公开(公告)号：US07643598B2
公开(公告)日：2010-01-05
申请号：US11204957
申请日：2005-08-16
申请人： Sang-Jin Byun , Hyun-Kyu Yu
发明人： Sang-Jin Byun , Hyun-Kyu Yu
IPC分类号： H04L7/00
CPC分类号： G01R23/10 , G01R23/005
摘要： Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.
摘要翻译：提供一种频率锁定检测器，其包括一个计数器和时钟数差分检测器，用于检测时钟数差，同时根据计数数N不增加复杂度，以比较相位彼此不同步的两个时钟信号的频率，并确定两个信号的频率之间的差异是否在期望的频率精度内。频率锁定检测器包括：用于对从外部输入的参考时钟信号的时钟数进行计数的计数器; 时钟数差检测器，用于检测参考时钟信号的时钟数与其相位与参考时钟信号的相位不同步的恢复时钟信号的时钟数之间的差; 以及锁定确定器，用于基于计数器和时钟数差分检测器的结果值来确定频率锁定。

24. 发明授权

US07626476B2 Multi-metal coplanar waveguide 有权
标题翻译：多金属共面波导
公开(公告)号：US07626476B2
公开(公告)日：2009-12-01
申请号：US11690219
申请日：2007-03-23
申请人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
发明人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
摘要翻译：提供了一种使用多层互连CMOS技术的共面波导CPW。在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。结果，可以提高超高频电路的性能并使电路小型化。

25. 发明授权

US07626473B2 Signal transmission line for millimeter-wave band 有权
标题翻译：毫米波段信号传输线
公开(公告)号：US07626473B2
公开(公告)日：2009-12-01
申请号：US11872026
申请日：2007-10-14
申请人： Ho Young Kim , Hae Cheon Kim , Hyun Kyu Yu , Young Jun Chong
发明人： Ho Young Kim , Hae Cheon Kim , Hyun Kyu Yu , Young Jun Chong
IPC分类号： H01P5/02 , H01P3/08
CPC分类号： H01P3/00
摘要： Provided is a signal transmission line for a millimeter-wave band. The signal transmission line includes: a dielectric substrate; an input line formed on the dielectric substrate; a pair of serial transmission lines formed on the dielectric substrate, the serial transmission lines being branched at, separated from, and electromagnetically connected in series with one end of the input line; a pair of parallel transmission lines respectively formed on the dielectric substrate at both sides of the input line and the serial transmission lines, and having both ends separated from and electromagnetically connected in parallel with one end of each of the input line and the serial transmission lines; and a pair of wires electrically connected between the other ends of the parallel transmission lines and a connection pad of a monolithic microwave integrated circuit (MMIC). An electrical signal of about 57 to 63 GHz generated from a monolithic microwave integrated circuit (MMIC) can be efficiently transferred.
摘要翻译：提供了一种用于毫米波段的信号传输线。信号传输线包括：电介质基片; 形成在电介质基板上的输入线; 形成在电介质基板上的一对串行传输线，串联传输线与输入线的一端分离并分离并与之电磁连接; 分别在输入线和串行传输线的两侧形成在电介质基板上的一对平行传输线，并且其两端与输入线和串行传输线的一端分开并与之并联电磁连接 ; 以及电连接在并行传输线的另一端之间的一对电线和单片微波集成电路（MMIC）的连接焊盘。可以有效地传送从单片微波集成电路（MMIC）产生的约57至63GHz的电信号。

26. 发明申请

US20090261481A1 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： WAFER LEVEL PACKAGE及其制作方法
公开(公告)号：US20090261481A1
公开(公告)日：2009-10-22
申请号：US12208512
申请日：2008-09-11
申请人： Jong Tae MOON , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
发明人： Jong Tae MOON , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
IPC分类号： H01L23/52 , H01L21/66 , H01L21/00
CPC分类号： H01L23/10 , B81B7/007 , B81C2203/0118 , H01L24/45 , H01L24/48 , H01L24/94 , H01L2224/16145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1461 , H01L2924/16235 , H01L2924/00 , H01L2924/2076 , H01L2224/05599
摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.
摘要翻译：提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要穿过基底的过程。因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

27. 发明申请

US20090225714A1 Apparatus and method for composing diversity subchannel in wireless communication system 有权
标题翻译：在无线通信系统中组合分集子信道的装置和方法
公开(公告)号：US20090225714A1
公开(公告)日：2009-09-10
申请号：US12381250
申请日：2009-03-10
申请人： Tae-Young Kim , Jeong-Ho Park , Dong-Seek Park , Hee-Won Kang , Ho-Kyu Choi , Jae-Weon Cho , Hyun-Kyu Yu , Su-Ryong Jeong
发明人： Tae-Young Kim , Jeong-Ho Park , Dong-Seek Park , Hee-Won Kang , Ho-Kyu Choi , Jae-Weon Cho , Hyun-Kyu Yu , Su-Ryong Jeong
IPC分类号： H04W72/04 , H04B7/02
CPC分类号： H04B7/12 , H04L5/0039 , H04L5/0041 , H04L5/0044 , H04L27/2602 , H04W72/04
摘要： An apparatus and a method for composing a subchannel in a wireless communication system are provided. The method includes performing a subband-based permutation on resources for composing a subchannel; selecting one or more subbands as resources for a band selection subchannel from the resources passing through the subband-based permutation; composing the band selection subchannel using at least one of the selected subbands; performing a resource allocation unit based permutation on resources not selected for the band selection subchannel; composing a resource allocation unit based diversity subchannel using subband remained in the selected subbands after the band selection subchannel is composed and at least one of the resource allocation units of the resources passing through the resource allocation unit based permutation; and composing a tone-based diversity subchannel by performing a tone-based permutation on resources remained after the resource allocation unit based diversity subchannel is composed.
摘要翻译：提供了一种用于在无线通信系统中组成子信道的装置和方法。该方法包括对用于构成子信道的资源执行基于子带的置换; 从经过基于子带的排列的资源中选择一个或多个子带作为用于频带选择子信道的资源; 使用所选择的子带中的至少一个来组成所述频带选择子信道; 对未选择用于所述频带选择子信道的资源执行基于资源分配单元的置换; 在组合频带选择子信道之后，使用子带保留在选择的子带中的资源分配单元的分集子信道的组合以及通过基于资源分配单元的排列的资源的资源分配单元中的至少一个; 以及通过对构成基于资源分配单元的分集子信道之后剩余的资源进行基于音调的置换来构成基于音调的分集子信道。

28. 发明申请

US20080129392A1 COLPITTS QUADRATURE VOLTAGE CONTROLLED OSCILLATOR 失效
标题翻译： COLPITTS QUADRATURE电压控制振荡器
公开(公告)号：US20080129392A1
公开(公告)日：2008-06-05
申请号：US11927957
申请日：2007-10-30
申请人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
IPC分类号： H03B27/00 , H03B5/12
CPC分类号： H03B5/1218 , H03B5/1231 , H03B2200/0074 , H03B2200/0078
摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.
摘要翻译：提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器可以实现。

29. 发明授权

US07372352B2 Transformer for varying inductance value 失效
标题翻译：变压器用于变化电感值
公开(公告)号：US07372352B2
公开(公告)日：2008-05-13
申请号：US11213552
申请日：2005-08-26
申请人： Young-Jae Lee , Cheon-Soo Kim , Hyun-Kyu Yu
发明人： Young-Jae Lee , Cheon-Soo Kim , Hyun-Kyu Yu
IPC分类号： H01F5/00
CPC分类号： H01F21/12 , H01F17/0006 , H01F19/08 , H01F21/08 , H01F2021/125 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： There is provided a transformer for varying an inductance value, which adjusts a tuning range of the inductance without decrease of the inductor's capability by selectively connecting switches to inductors and controls an amount of magnetic flux. And the transformer consists of multiple inductors formed on a semiconductor substrate, which including N number of metal lines, N number of ports made by twisting the metal lines in the form of a symmetric circuit, wherein a certain number of ports among the N number of ports, which are connected to switch elements.
摘要翻译：提供了用于改变电感值的变压器，其通过选择性地将开关连接到电感器并控制磁通量来调节电感的调谐范围而不降低电感器的能力。并且，所述变压器由形成在半导体基板上的多个电感器组成，所述多个电感器包括N个金属线，N个通过以对称电路的形式扭转所述金属线而制成的端口，其中，N个端口，连接到交换机元件。

30. 发明申请

US20070134852A1 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method 有权
标题翻译：半导体集成电路电源线布局方法和半导体集成电路布局方法
公开(公告)号：US20070134852A1
公开(公告)日：2007-06-14
申请号：US11523212
申请日：2006-09-19
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H01L21/82
CPC分类号： H01L27/0207
摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
摘要翻译：提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化可以防止到去耦电容器的电源线。

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