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21. 发明申请

US20090021994A1 MEMORY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：用于编程其的存储器和方法
公开(公告)号：US20090021994A1
公开(公告)日：2009-01-22
申请号：US11779951
申请日：2007-07-19
申请人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho , Wen-Chiao Ho
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.
摘要翻译：一种用于编程存储器的方法，包括多个具有左半单元和右半单元的多级单元，包括以下步骤。首先，提供与要存储的2n组数据对应的目标地址，其中n是正整数。接下来，基于编程循环中的目标地址，将2n组数据顺序地编程到多电平单元中，使得存储在左半单元中的数据和存储在右半单元中的数据来自不同的组 2n组数据。

22. 发明授权

US07474565B2 Programming scheme for non-volatile flash memory 有权
标题翻译：非易失性闪存的编程方案
公开(公告)号：US07474565B2
公开(公告)日：2009-01-06
申请号：US11636920
申请日：2006-12-11
申请人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
发明人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.
摘要翻译：本发明的一个实施例涉及一种编程存储器单元的方法。存储单元处于具有最大初始阈值电压的第一状态。存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。在最大初始阈值电压和目标阈值电压之间存在一个提示电压。存储单元具有漏极区域。该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度宽度到第二个脉冲宽度。第二脉冲宽度小于第一脉冲宽度。

23. 发明授权

US08456906B2 Memory and operation method therefor 有权
标题翻译：记忆和操作方法
公开(公告)号：US08456906B2
公开(公告)日：2013-06-04
申请号：US13306678
申请日：2011-11-29
申请人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
发明人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/349
摘要： An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.
摘要翻译：一种具有多个存储单元的存储器件的操作方法，包括：通过第一字线电压读取多个存储器单元以获得第一数量的第一逻辑状态; 通过第二字线电压读取多个存储器单元以获得第二数量的第一逻辑状态，第二字线电压不同于第一字线电压; 并且如果第一逻辑状态的第一数目等于第一逻辑状态的第二数量，则使用第二字线电压作为目标字线电压。

24. 发明授权

US08259484B2 3D chip selection for shared input packages 有权
标题翻译：共享输入包的3D芯片选择
公开(公告)号：US08259484B2
公开(公告)日：2012-09-04
申请号：US12768620
申请日：2010-04-27
申请人： Chun-Hsiung Hung , Hsin-Yi Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho
IPC分类号： G11C5/06
CPC分类号： G11C8/12 , G11C5/02 , Y10T29/49002
摘要： A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process.
摘要翻译：具有共享输入和唯一访问ID的芯片的多芯片封装。一个独特的第一个ID被分配并存储在模具中的裸片上。一组芯片安装在多芯片封装中。通过在共享输入上应用一系列扫描ID来分配自由访问ID。在每个管芯上，将共享输入上的扫描ID与存储在管芯上的唯一的第一个ID进行比较。在检测到匹配时，芯片上的电路被使能一段时间以将访问ID写入非易失性存储器中，从而一次启用多芯片封装中的一个管芯。此外，共享输入用于在集合中的一个启用的裸片上的非易失性存储器中写入可用访问ID。唯一的第一个ID可以在晶片级分类过程中存储。

25. 发明授权

US08239619B2 Method and apparatus for high-speed byte-access in block-based flash memory 有权
标题翻译：用于基于块的闪速存储器中的高速字节访问的方法和装置
公开(公告)号：US08239619B2
公开(公告)日：2012-08-07
申请号：US12833305
申请日：2010-07-09
申请人： Chun-Hsiung Hung , Hsin-Yi Ho , Hsiang-Pang Li
发明人： Chun-Hsiung Hung , Hsin-Yi Ho , Hsiang-Pang Li
IPC分类号： G06F12/00 , G06F9/26
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.
摘要翻译：利用一次擦除一次程序的渐进式索引结构的技术管理闪速存储器件中的数据，这避免了每次更新存储在闪速存储器件中的数据时执行扇区擦除操作。结果，在需要扇区擦除操作之前可以执行大量写入操作。因此，基于块的闪存可用于高速字节访问。

26. 发明授权

US08189357B2 Memory with multiple reference cells 有权
标题翻译：具有多个参考单元的内存
公开(公告)号：US08189357B2
公开(公告)日：2012-05-29
申请号：US12555872
申请日：2009-09-09
申请人： Hsin-Yi Ho , Chia-Ching Li
发明人： Hsin-Yi Ho , Chia-Ching Li
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C11/56 , G11C11/5642 , G11C2211/5634
摘要： A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
摘要翻译：存储器包括存储器阵列，读出放大器和参考电路。存储器阵列包括存储器单元。读出放大器包括耦合到存储单元的第一端子和第二端子。参考电路包括第一参考单元，第二参考单元和开关。第一参考单元具有用于基于第一参考字线电压提供第一参考电流的第一参考阈值电压。第二参考单元具有第二参考阈值电压，用于基于第二参考字线电压提供第二参考电流。响应于控制信号，开关选择性地将第一和第二参考电流中的一个提供给第二端子。第一和第二参考字线电压对应于不同的电压电平。

27. 发明申请

US20120069671A1 MEMORY AND OPERATION METHOD THEREFOR 有权
标题翻译：其记忆和操作方法
公开(公告)号：US20120069671A1
公开(公告)日：2012-03-22
申请号：US13306678
申请日：2011-11-29
申请人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
发明人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
IPC分类号： G11C16/26
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/349
摘要： An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state.
摘要翻译：一种具有多个存储单元的存储器件的操作方法，包括：通过第一字线电压读取多个存储器单元以获得第一数量的第一逻辑状态; 通过第二字线电压读取多个存储器单元以获得第二数量的第一逻辑状态，第二字线电压不同于第一字线电压; 并且如果第一逻辑状态的第一数目等于第一逻辑状态的第二数量，则使用第二字线电压作为目标字线电压。

28. 发明授权

US08045403B2 Programming method and memory device using the same 有权
标题翻译：编程方法和使用相同的存储设备
公开(公告)号：US08045403B2
公开(公告)日：2011-10-25
申请号：US12943443
申请日：2010-11-10
申请人： Chun-Hsiung Hung , Hsin-Yi Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho
IPC分类号： G11C7/00
CPC分类号： G11C16/3404 , G11C16/3454
摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.
摘要翻译：提供了一种应用于存储器的编程方法。存储器包括多个存储单元。该方法包括以下步骤。响应于第一编程命令对存储器单元的目标单元进行编程。响应于第二编程命令对目标单元进行编程。

29. 发明申请

US20110157951A1 3D CHIP SELECTION FOR SHARED INPUT PACKAGES 有权
标题翻译：用于共享输入包的3D芯片选择
公开(公告)号：US20110157951A1
公开(公告)日：2011-06-30
申请号：US12768620
申请日：2010-04-27
申请人： CHUN-HSIUNG HUNG , Hsin-Yi Ho
发明人： CHUN-HSIUNG HUNG , Hsin-Yi Ho
IPC分类号： G11C5/06 , H05K13/00 , G11C7/00
CPC分类号： G11C8/12 , G11C5/02 , Y10T29/49002
摘要： A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process.
摘要翻译：具有共享输入和唯一访问ID的芯片的多芯片封装。一个独特的第一个ID被分配并存储在模具中的裸片上。一组芯片安装在多芯片封装中。通过在共享输入上应用一系列扫描ID来分配自由访问ID。在每个管芯上，将共享输入上的扫描ID与存储在管芯上的唯一的第一个ID进行比较。在检测到匹配时，芯片上的电路被使能一段时间以将访问ID写入非易失性存储器中，从而一次启用多芯片封装中的一个管芯。此外，共享输入用于在集合中的一个启用的裸片上的非易失性存储器中写入可用访问ID。唯一的第一个ID可以在晶片级分类过程中存储。

30. 发明申请

US20100302863A1 Reading Method for MLC Memory and Reading Circuit Using the Same 有权
标题翻译：使用相同的MLC存储器和读取电路的读取方法
公开(公告)号：US20100302863A1
公开(公告)日：2010-12-02
申请号：US12855799
申请日：2010-08-13
申请人： Hsin-Yi Ho , Ji-Yu Hung
发明人： Hsin-Yi Ho , Ji-Yu Hung
IPC分类号： G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C16/3427
摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
摘要翻译：多级单元（MLC）存储器的读取方法包括以下步骤。多个字线电压被顺序提供给MLC存储单元。对应于字线电压的多个位线电压被依次提供给MLC存储单元。字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压字线电压。

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