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21. 发明申请

US20050027963A1 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache 失效
标题翻译：用于使用进程标识符来最小化线性寻址高速缓存中的混叠的系统和方法
公开(公告)号：US20050027963A1
公开(公告)日：2005-02-03
申请号：US10917449
申请日：2004-08-13
申请人： Herbert Hum , Stephan Jourdan , Per Hammarlund
发明人： Herbert Hum , Stephan Jourdan , Per Hammarlund
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1054 , G06F12/1063 , G06F12/109
摘要： A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.
摘要翻译：描述了用于减少线性地址混叠的系统和方法。在一个实施例中，线性地址的一部分与进程标识符（例如，页目录基本指针）组合以形成调整后的线性地址。页面目录基本指针对于进程是唯一的，并且将其与线性地址的一部分组合产生调整的线性地址，其提供没有别名的高概率。调整后的线性地址的一部分用于搜索由线性地址指定的数据块的经调整的线性寻址高速缓冲存储器。如果数据块不在调整后的线性寻址高速缓冲存储器中，则替换策略选择调整后的线性寻址高速缓存存储器中的一条高速缓存行，并用数据块替换所选择的高速缓存线的数据块位于从翻译线性地址产生的物理地址。所选择的高速缓存线的标签是调整后的线性地址的一部分和通过转换线性地址产生的物理地址。

22. 发明授权

US06798364B2 Method and apparatus for variable length coding 有权
标题翻译：用于可变长度编码的方法和装置
公开(公告)号：US06798364B2
公开(公告)日：2004-09-28
申请号：US10068050
申请日：2002-02-05
申请人： Yen-Kuang Chen , Matthew J. Holliman , Herbert Hum , Per H. Hammarlund , Thomas Huff , William W. Macy
发明人： Yen-Kuang Chen , Matthew J. Holliman , Herbert Hum , Per H. Hammarlund , Thomas Huff , William W. Macy
IPC分类号： H03M740
CPC分类号： H03M7/46 , G11B20/1426 , H03M5/145 , H03M7/40 , H04N19/13 , H04N19/29 , H04N19/34 , H04N19/36 , H04N19/63
摘要： A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.
摘要翻译：描述了用于可变长度编码的方法和装置。一种方法包括：接收一组具有一组设定值的数据，识别所述数据组内的所述组中的组的位置组，而不分支，对于所述一组位置中的每一个，编码非设定值的运行在每组职位之前。

23. 发明申请

US20160370852A1 Distribution of Tasks Among Asymmetric Processing Elements 审中-公开
公开(公告)号：US20160370852A1
公开(公告)日：2016-12-22
申请号：US15256050
申请日：2016-09-02
申请人： HERBERT HUM , ERIC SPRANGLE , DOUG CARMEAN , RAJESH KUMAR
发明人： HERBERT HUM , ERIC SPRANGLE , DOUG CARMEAN , RAJESH KUMAR
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

24. 发明授权

US08151096B2 Method to improve branch prediction latency 有权
标题翻译：提高分支预测延迟的方法
公开(公告)号：US08151096B2
公开(公告)日：2012-04-03
申请号：US12187126
申请日：2008-08-06
申请人： Herbert Hum , Hongliang Gao
发明人： Herbert Hum , Hongliang Gao
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3844
摘要： An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.
摘要翻译：至少部分地基于先前分支指令的地址生成指令的分支预测的装置，其中先前指令在程序顺序中指令之前。预测还可以基于相对于先前分支指令的分支历史值和一个或多个先前分支预测。

25. 发明授权

US07958336B2 System and method for reservation station load dependency matrix 有权
标题翻译：保留站负载依赖矩阵的系统和方法
公开(公告)号：US07958336B2
公开(公告)日：2011-06-07
申请号：US12164666
申请日：2008-06-30
申请人： Sagi Lahav , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
发明人： Sagi Lahav , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/3017 , G06F9/3834 , G06F9/384 , G06F9/3859
摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.
摘要翻译：设备和方法可以获取用于执行的指令或微操作。可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。可以存储对应于第一指令所依赖的每个源值的值。可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。可以在与指令相关联的存储值表示满足依赖性之后执行指令。

26. 发明申请

US20100037036A1 METHOD TO IMPROVE BRANCH PREDICTION LATENCY 有权
标题翻译：改进分支预测延迟的方法
公开(公告)号：US20100037036A1
公开(公告)日：2010-02-11
申请号：US12187126
申请日：2008-08-06
申请人： Herbert Hum , Hongliang Gao
发明人： Herbert Hum , Hongliang Gao
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3844
摘要： An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.
摘要翻译：至少部分地基于先前分支指令的地址生成指令的分支预测的装置，其中先前指令在程序顺序中指令之前。预测还可以基于相对于先前分支指令的分支历史值和一个或多个先前分支预测。

27. 发明申请

US20090077360A1 Software constructed stands for execution on a multi-core architecture 有权
标题翻译：构建的软件代表在多核架构上执行
公开(公告)号：US20090077360A1
公开(公告)日：2009-03-19
申请号：US11901644
申请日：2007-09-18
申请人： Wei Liu , Lixin Su , Youfeng Wu , Herbert Hum
发明人： Wei Liu , Lixin Su , Youfeng Wu , Herbert Hum
IPC分类号： G06F9/44 , G06F9/38
CPC分类号： G06F8/433
摘要： In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种形成指令串的软件控制方法。软件可以包括用于获得包括多个基本块的超级块的代码的指令，为代码构建依赖性有向非循环图（DAG），将依赖性DAG的边缘耦合的分类节点排列成拓扑顺序，从节点形成线基于硬件约束，规则约束和调度约束，并且生成链的可执行代码并将可执行代码存储在存储器中。描述和要求保护其他实施例。

28. 发明申请

US20090019306A1 Protecting tag information in a multi-level cache hierarchy 审中-公开
标题翻译：保护多级缓存层次结构中的标签信息
公开(公告)号：US20090019306A1
公开(公告)日：2009-01-15
申请号：US11827197
申请日：2007-07-11
申请人： Herbert Hum , Rajagopal K. Narayanan
发明人： Herbert Hum , Rajagopal K. Narayanan
IPC分类号： G06F11/00
CPC分类号： G06F12/0811 , G06F11/1064 , G06F2212/1032 , Y02D10/13
摘要： In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括与其耦合的其它高速缓冲存储器包含的共享高速缓存存储器。共享高速缓冲存储器包括纠错逻辑，用于校正存在于其它高速缓存存储器之一的标签阵列中的错误，并提供校正标签信息以替换包括错误的标签阵列中的标签条目。描述和要求保护其他实施例。

29. 发明申请

US20070022279A1 Compressing and accessing a microcode ROM 有权
标题翻译：压缩和访问微码ROM
公开(公告)号：US20070022279A1
公开(公告)日：2007-01-25
申请号：US11186240
申请日：2005-07-20
申请人： Youfeng Wu , Sangwook Kim , Mauricio Breternitz , Herbert Hum
发明人： Youfeng Wu , Sangwook Kim , Mauricio Breternitz , Herbert Hum
IPC分类号： G06F9/44
CPC分类号： G06F12/06 , G06F8/4436 , G06F9/30178 , G06F2212/401
摘要： An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.
摘要翻译：提供了一种用于在处理器中压缩微代码ROM（“uROM”）并有效访问压缩的“uROM”的装置。可以使用基于聚类的方法来有效地压缩uROM。该方法将相似的微代码列组合成不同的集群，并识别每个集群内的唯一模式。每个集群中唯一标识的模式都存储在模式存储中。帮助将从uROM获取的微代码字（“uOP”）的地址映射到uOP所需的唯一模式的索引可以存储在索引存储器中。通常，从压缩的uROM获取uop比从未压缩的uROM获取更长的时间。压缩的uROM可以被设计成使得从压缩的uROM获取uop（或uop）的过程可以被完全流水线化以减少访问等待时间。

30. 发明申请

US20060253657A1 Hierarchical directories for cache coherency in a multiprocessor system 失效
标题翻译：多处理器系统中高速缓存一致性的分层目录
公开(公告)号：US20060253657A1
公开(公告)日：2006-11-09
申请号：US11482673
申请日：2006-07-06
申请人： Herbert Hum , James Goodman
发明人： Herbert Hum , James Goodman
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/0813
摘要： Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.
摘要翻译：使用导入缓存和/或导出目录与其中的代理来响应数据请求。导入缓存存储通过代理程序导入的数据。导出目录存储与通过代理导出的数据相关的信息。因为导入缓存和导出目录只存储已经通过代理的数据，所以并不是系统中传输的所有数据都被单个导入缓存或导出目录跟踪。

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