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21. 发明申请

US20050188277A1 Timeout event trigger generation 有权
标题翻译：超时事件触发器生成
公开(公告)号：US20050188277A1
公开(公告)日：2005-08-25
申请号：US10783112
申请日：2004-02-20
申请人： Michael Tayler , Eric Delano
发明人： Michael Tayler , Eric Delano
IPC分类号： G06F1/14 , G06F11/00 , G06F11/30
CPC分类号： G06F11/076
摘要： A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system also includes a plurality of trigger generators corresponding to the plurality of kinds of timeout events. Each of the plurality of trigger generators is associated with a corresponding timeout threshold value representing the minimum amount of time that must elapse for the trigger generator to generate a timeout event trigger. For each of the plurality of timeout triggers, a corresponding selection signal selects one of the plurality of periodic overflow signals. The timeout threshold corresponding to each timeout trigger is equal to the period of the corresponding selected overflow signal multiplied by the value of the corresponding control signal.
摘要翻译：公开了用于响应于多种超时事件而产生多个超时事件触发的系统。该系统包括溢出发生器，其产生具有多个周期的多个溢出信号。该系统还包括与多种超时事件对应的多个触发发生器。多个触发发生器中的每一个与相应的超时阈值相关联，该阈值表示触发器产生器必须经过的生成超时事件触发的最小时间量。对于多个超时触发中的每一个，相应的选择信号选择多个周期性溢出信号中的一个。对应于每个超时触发的超时阈值等于对应的所选溢出信号乘以相应控制信号的值的周期。

22. 发明授权

US06820167B2 Configurable crossbar and related methods 失效
标题翻译：可配置的交叉开关和相关方法
公开(公告)号：US06820167B2
公开(公告)日：2004-11-16
申请号：US10147193
申请日：2002-05-16
申请人： Samuel David Naffziger , Eric DeLano
发明人： Samuel David Naffziger , Eric DeLano
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： A processing system crossbar includes control sub-ports and mini-ports selectively configurable as connection points. Each control sub-port has a domain of mini-ports that the control sub-port is configured to selectively control. Each mini-port is configurable to select a control sub-port from those having domains that include the selecting mini-port. Each connection point includes a corresponding control sub-port and each mini-port selecting the corresponding control sub-port. The crossbar provides bandwidth tailored for various system agents. Thus crossbar bottlenecks are eliminated or reduced.
摘要翻译：处理系统横杆包括可选择性地配置为连接点的控制子端口和小型端口。每个控制子端口具有控制子端口配置为选择性控制的小型端口的域。每个迷你端口都可配置为从具有选择小型端口的域中选择一个控制子端口。每个连接点包括相应的控制子端口和每个微型端口选择相应的控制子端口。交叉开关为各种系统代理提供量身定制的带宽。因此，横向瓶颈被消除或减少。

23. 发明授权

US08799586B2 Memory mirroring and migration at home agent 有权
标题翻译：内部镜像和迁移在本地代理
公开(公告)号：US08799586B2
公开(公告)日：2014-08-05
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

24. 发明授权

US08782347B2 Controllably exiting an unknown state of a cache coherency directory 有权
标题翻译：可控退出高速缓存一致性目录的未知状态
公开(公告)号：US08782347B2
公开(公告)日：2014-07-15
申请号：US12492280
申请日：2009-06-26
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric DeLano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric DeLano , Gregory S. Averill
IPC分类号： G06F13/28 , G06F12/08 , G06F9/50
CPC分类号： G06F12/0817 , G06F9/5033 , G06F2212/1032
摘要： In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，并且如果与请求相关联的目录条目处于未知状态，则向至少一个其他高速缓存代理发送无效侦听消息以使高速缓存中的信息无效与读取请求的位置相对应的其他高速缓存代理的位置，以使目录项进入已知状态。描述和要求保护其他实施例。

25. 发明授权

US08171121B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US08171121B2
公开(公告)日：2012-05-01
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

26. 发明申请

US20090019267A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 有权
公开(公告)号：US20090019267A1
公开(公告)日：2009-01-15
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
IPC分类号： G06F15/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

27. 发明申请

US20070067602A1 Mitigating context switch cache miss penalty 有权
标题翻译：减轻上下文切换缓存未命中
公开(公告)号：US20070067602A1
公开(公告)日：2007-03-22
申请号：US11228058
申请日：2005-09-16
申请人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
发明人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0842
摘要： Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
摘要翻译：描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到到处理器。

28. 发明授权

US07028167B2 Core parallel execution with different optimization characteristics to decrease dynamic execution path 有权
公开(公告)号：US07028167B2
公开(公告)日：2006-04-11
申请号：US10091084
申请日：2002-03-04
申请人： Donald C. Soltis, Jr. , Eric Delano
发明人： Donald C. Soltis, Jr. , Eric Delano
IPC分类号： G06F11/00
CPC分类号： G06F9/3891 , G06F9/3842 , G06F9/3851 , G06F9/3853 , G06F9/3885
摘要： The invention provides a processor with two or more parallel instruction paths for processing instructions. The instruction paths may be implemented with a plurality of cores on a common die. Instructions of the invention are preferably processed within a bundle of two or more instructions of a common program thread; and each of the instruction paths preferably forms a cluster to process bundled instructions. Each of the instruction paths has an array of pipelined execution units. Initially, two or more of the parallel instruction paths processes the same program thread (one or more bundles) through the execution units, but with different optimization characteristics set for each path. Assessment logic monitors the processing of the initial program thread through the execution units and selects the heuristics defining which path is in the lead. The other instruction paths are then reallocated, or synchronized, with the optimization characteristics of the lead instruction path, or with similarly optimized characteristics, to process other bundles of the program thread; preferably, the lead path continues processing of the initial thread without being disturbed. For other program threads, the process may repeat in processing like bundles through multiple instruction paths to identify the preferred heuristics; and then synchronizing the multiple instruction paths to the optimized characteristics to improve per thread performance.

29. 发明申请

US20060031672A1 Resource protection in a computer system with direct hardware resource access 审中-公开
标题翻译：具有直接硬件资源访问的计算机系统中的资源保护
公开(公告)号：US20060031672A1
公开(公告)日：2006-02-09
申请号：US10910630
申请日：2004-08-03
申请人： Donald Soltis , Rohit Bhatia , Eric DeLano , Bill Greene , Amy Santoni
发明人： Donald Soltis , Rohit Bhatia , Eric DeLano , Bill Greene , Amy Santoni
IPC分类号： H04L9/00
CPC分类号： G06F21/6281 , G06F12/1027 , G06F12/1491 , G06F2221/2105
摘要： In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.
摘要翻译：在本发明的一个实施例中，提供了一种在包括多个资源的计算机系统中使用的计算机实现的方法。多个资源包括受保护的资源和不受保护的资源。未受保护的资源包括关键资源和非关键资源。该方法包括以下步骤：（A）从软件程序接收访问指定的一个未受保护的资源的请求; （B）如果计算机系统以非保护操作模式运行，则授予请求; 以及（C）如果所述计算机系统以受保护的操作模式操作，则如果所述计算机系统未在受保护的诊断操作模式下操作，则执行拒绝所述请求的步骤。

30. 发明授权

US06895497B2 Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority 失效
标题翻译：多分配CPU集成电路具有虚拟化和模块化资源，可调整调度优先级
公开(公告)号：US06895497B2
公开(公告)日：2005-05-17
申请号：US10092714
申请日：2002-03-06
申请人： Eric S. Fetzer , Wayne Kever , Eric DeLano
发明人： Eric S. Fetzer , Wayne Kever , Eric DeLano
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.
摘要翻译：多调度处理器具有多个指令获取单元，每个指令提取单元用于向指令解码和调度单元提供指令流。处理器还具有资源分配单元，以及多个资源，例如组合的整数和地址执行管线和浮点执行管线。每个指令解码和调度单元请求执行资源分配单元的指令所需的资源，该指令在多个指令解码和调度单元之间进行仲裁。

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