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21. 发明授权

US07769955B2 Multiple thread instruction fetch from different cache levels 有权
标题翻译：从不同的缓存级别获取多线程指令
公开(公告)号：US07769955B2
公开(公告)日：2010-08-03
申请号：US11790811
申请日：2007-04-27
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3802 , G06F9/3851 , G06F12/0897
摘要： A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
摘要翻译：提供了一种数据处理装置，其中处理电路执行包括至少一个高优先级线程和至少一个较低优先级线程的多个程序线程。从包含多个高速缓存级别的缓存存储器层次中检索线程所需的指令。所述高速缓存存储器层级包括旁路路径，用于在执行所需指令的查找过程时省略所述高速缓存存储器层级的预定级别，以及当将所述所需指令返回给所述处理电路时绕过所述高速缓存存储器层级的所述预定级别。当请求的指令用于较低优先级的线程时，默认使用旁路路径。

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