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    • 21. 发明授权
    • Method and apparatus for programming non-volatile data storage device
    • 用于编程非易失性数据存储设备的方法和装置
    • US07589999B2
    • 2009-09-15
    • US11713638
    • 2007-03-05
    • Seong-hun JeongHoung-sog MinDong-woo LeeShin-wook KangHyang-suk Park
    • Seong-hun JeongHoung-sog MinDong-woo LeeShin-wook KangHyang-suk Park
    • G11C11/34
    • G11C16/102G11C2216/14
    • A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.
    • 提供了一种用于对非易失性数据存储装置进行编程的方法和装置,其中当以非法数据存储装置的方式执行写入操作时,可以使用包括在非易失性数据存储装置中的多个页缓冲器执行快速写入操作 使用多个非易失性数据存储设备在多信道系统中对每个信道进行交织。 该方法包括使用从非易失性数据存储装置中包括的多个页缓冲器中选择的页缓冲器来编程包括在非易失性数据存储装置中的存储单元阵列中的数据,并执行用于使用另一个装载数据加载数据的设置操作 页面缓冲区,与编程期间选择的页面缓冲区不同。
    • 23. 发明申请
    • SYSTEM AND DEVICE HAVING ALTERNATIVE BIT ORGANIZATION
    • 具有替代性组织的系统和设备
    • US20080301392A1
    • 2008-12-04
    • US12127148
    • 2008-05-27
    • Dong-woo LEE
    • Dong-woo LEE
    • G06F12/00
    • G06F13/4213
    • A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and second memory devices via a command/address bus, and is connected to the first memory device via a data bus separate from the command/address bus and having an upper half and a lower half. However, the CPU is connected to the second memory device via only the upper half of the data bus.
    • 公开了一种系统,其包括可根据第一位组织或第二位组织操作的第一存储器设备,仅根据第一位组织可操作的第二存储器件以及中央处理单元(CPU)。 CPU通常经由命令/地址总线连接到第一和第二存储器件,并且经由与命令/地址总线分离并具有上半部分和下半部分的数据总线连接到第一存储器件。 然而,CPU仅通过数据总线的上半部连接到第二存储器件。
    • 24. 发明申请
    • Text Input System and Method Based on Voice Recognition
    • 基于语音识别的文本输入系统和方法
    • US20080270128A1
    • 2008-10-30
    • US12092790
    • 2006-08-14
    • Dong-Woo LeeJun-Seok ParkDong-Won HanIl-Yeon Cho
    • Dong-Woo LeeJun-Seok ParkDong-Won HanIl-Yeon Cho
    • G10L15/00
    • G06F3/16G10L15/07G10L15/08
    • Provided is a text input system and method based on voice recognition. The system includes: an input unit for receiving part of text, i.e., partial text; a voice input unit for receiving entire text of the partial text by voice; a voice recognition preprocessing unit for analyzing the voice inputted through the voice input unit and transmitting the partial text inputted through the input unit with voice analysis information; a voice recognizing unit for creating a list of a recognition candidates by using the partial text transmitted from the voice recognition preprocessing unit, performing a voice recognition and selecting a text among the recognition candidates; and an output unit for outputting a finally voice recognized text.
    • 提供了一种基于语音识别的文本输入系统和方法。 该系统包括:用于接收部分文本的输入单元,即部分文本; 语音输入单元,用于通过语音接收部分文本的整个文本; 语音识别预处理单元,用于分析通过语音输入单元输入的语音,并通过语音分析信息发送通过输入单元输入的部分文本; 语音识别单元,用于通过使用从语音识别预处理单元发送的部分文本来创建识别候选者的列表,执行语音识别并在识别候选中选择文本; 以及用于输出最终语音识别文本的输出单元。
    • 25. 发明申请
    • Methods of communicating data using inversion and related systems
    • 使用反演和相关系统传递数据的方法
    • US20080162778A1
    • 2008-07-03
    • US11818165
    • 2007-06-13
    • Jung-yong ChoiDong-woo Lee
    • Jung-yong ChoiDong-woo Lee
    • G06F12/00
    • G06F13/4217Y02D10/14Y02D10/151
    • A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed.
    • 可以提供一种方法,以通过数据总线与每组输出数据位和每组输入数据位具有相等的数据宽度来传送表示相应多组输入数据位的多组输出数据位。 多个输入数据组中的每一组可以在数据寄存器处被接收。 对于在数据寄存器处接收的每组输入数据位,如果具有第一逻辑电平的输入数据位组组中的数据位的数目大于数据宽度的一半,则输入数据位组被反转, 输出数据位的反相组作为数据总线上的并行输出数据位组发送,并且发送与各组输出数据位相关联的反转标志。 对于在数据寄存器处接收的每组输入数据位,如果具有与第一逻辑电平不同的第二逻辑电平的输入数据位组组中的数据位数大于数据宽度的一半,则输入组 数据位在数据总线上并行发送而不反转为相应的输出数据位组,并且发送与各组输出数据位相关联的非反转标志。 还讨论了相关系统。
    • 27. 发明授权
    • Packet addressing programmable dual port memory devices and related methods
    • 分组寻址可编程双端口存储器件及相关方法
    • US07196962B2
    • 2007-03-27
    • US10937519
    • 2004-09-09
    • Dong-Woo Lee
    • Dong-Woo Lee
    • G11C7/10G11C11/4093G11C11/4096G11C8/12
    • G11C8/06
    • In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory cell data output from the selected memory blocks are sequentially output to the selected data I/O pads, and data input to the selected data I/O pads are sequentially input to the selected memory blocks, so that read and write operations are independently accomplished in each of data I/O pads. The data I/O width can be adjusted according to the word length which is selectively set up, and power consumption can be reduced due to partial activation of the memory block.
    • 在分组寻址方法中,从多个存储器块中选择一个或多个存储器块,并且从多个数据I / O焊盘中选择一个或多个数据I / O焊盘,通过该数据I / O焊盘输入或输出数据 存储器块被加载,从所选择的存储器块输出的存储单元数据被顺序地输出到选择的数据I / O焊盘,并且输入到所选择的数据I / O焊盘的数据被顺序地输入到所选择的存储器块, 在每个数据I / O焊盘中独立地实现写入操作。 数据I / O宽度可以根据有选择地设置的字长进行调整,由于存储块的部分激活,能够降低功耗。