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    • 23. 发明授权
    • VCXO with reduced PWM effects high slew rate conditions
    • VCXO具有降低PWM效应的高转换速率条件
    • US06181217B2
    • 2001-01-30
    • US09353221
    • 1999-07-14
    • David Glenn White
    • David Glenn White
    • H03B532
    • H03B5/32H03B5/36H03B5/368
    • A VCXO having reduced PWM effects includes an inverter (U1) having a DC feedback path (Rf) for biasing the inverter to a linear operating range and having an AC feedback path (40) for causing oscillations to occur and for varying the frequency of said oscillations in accordance with a frequency control bias voltage, Vbias. The AC feedback path includes a tank circuit (28) comprising a crystal (X1) having a first plate (22) coupled to an output (2) of the inverter via a source resistance (Rx), coupled to a source of reference potential via a varactor diode (D1) and coupled to a source (R1,T2) of the bias voltage (Vbias). The crystal (X1) has a second plate (24) coupled to an input of the inverter and coupled to the source of reference potential via a capacitor (C2) of fixed value. The source resistance is of a relatively high value selected to substantially attenuate the bias voltage whereby both the input and the output terminals of the inverter are effectively isolated from the bias voltage source. Advantageously, the PWM effect is reduced, the tuning range is extended and crystal power dissipation is reduced.
    • 具有降低的PWM效应的VCXO包括具有DC反馈路径(Rf)的逆变器(U1),用于将逆变器偏置到线性工作范围并且具有用于引起振荡发生的AC反馈路径(40),并且用于改变所述 根据频率控制偏置电压Vbias进行振荡。 交流反馈路径包括一个包括晶体(X1)的储能电路(28),该晶体(X1)具有经由源极电阻(Rx)耦合到反相器的输出端(2)的第一板(22),耦合到参考电位源 变容二极管(D1)并耦合到偏置电压(Vbias)的源极(R1,T2)。 晶体(X1)具有耦合到反相器的输入的第二板(24),并通过固定值的电容器(C2)耦合到参考电位源。 源电阻具有相对较高的值,其被选择为基本上衰减偏置电压,由此反相器的输入端和输出端都有效地与偏置电压源隔离。 有利地,PWM效应降低,调谐范围扩大并且晶体功率消耗降低。