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21. 发明申请

US20100058428A1 BROADCAST RECEIVING APPARATUS CAPABLE OF COMMUNICATING WITH EXTERNAL APPARATUS AND METHOD FOR USING CONTENT 审中-公开
标题翻译：能够与外部设备通信的广播接收设备和使用内容的方法
公开(公告)号：US20100058428A1
公开(公告)日：2010-03-04
申请号：US12370847
申请日：2009-02-13
申请人： Chi-won KIM
发明人： Chi-won KIM
IPC分类号： H04N7/173
CPC分类号： H04N5/44 , H04N5/63 , H04N21/4126 , H04N21/4131 , H04N21/4334 , H04N21/43615
摘要： A broadcast receiving apparatus capable of communicating with an external apparatus, and a method for using content in the broadcast receiving apparatus are provided. The broadcast receiving apparatus transmits a broadcast signal corresponding to content, a user desires to receive, to the external apparatus, and the user turns off a display unit of the broadcast receiving apparatus using the external apparatus. Therefore, it is possible for the user to use desired content regardless of location and time, and it is also possible to prevent power from being consumed unnecessarily.
摘要翻译：提供能够与外部装置通信的广播接收装置，以及广播接收装置中使用内容的方法。广播接收装置向外部设备发送与用户希望接收的内容相对应的广播信号，并且用户使用外部设备关闭广播接收设备的显示单元。因此，无论位置和时间如何，用户都可以使用期望的内容，并且还可以防止不必要地消耗电力。

22. 发明申请

US20070046350A1 Pre-emphasis circuit including slew rate controllable buffer 有权
标题翻译：预加重电路包括压摆率可控缓冲器
公开(公告)号：US20070046350A1
公开(公告)日：2007-03-01
申请号：US11506652
申请日：2006-08-18
申请人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
发明人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
IPC分类号： H03K5/12
CPC分类号： H03K6/04
摘要： A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
摘要翻译：一种能够控制从缓冲器输出的信号的转换速率的预加重电路，该缓冲器将输出信号传送到输出驱动器以增加可控电压步长的范围包括第一缓冲器，第二缓冲器和输出驱动器。第一缓冲器缓冲具有彼此相反的相位的第一和第二主输入信号，输出第一和第二主输出信号，并且使用至少一个主控制信号来控制第一和第二主输出信号的转换速率。第二缓冲器缓冲具有彼此相反相位的第一和第二子输入信号，输出第一和副输出信号，并且使用至少一个子控制信号来控制第一和第二子输出信号的转换速率。输出驱动器使用至少两个控制信号和第一和第二缓冲器的输出信号产生具有相反相位的第一和第二输出信号。

23. 发明申请

US20050024243A1 Serializer and method of serializing parallel data into serial data stream 失效
公开(公告)号：US20050024243A1
公开(公告)日：2005-02-03
申请号：US10770491
申请日：2004-02-04
申请人： Chi-Won Kim
发明人： Chi-Won Kim
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A serializer serializes N data (N>2) in N stages into a serial data stream. Each stage includes a logic section and a first inverter. The logic section receives i-th data (where i is less than or equal to N) of the N parallel data to output the i-th data or inverted i-th data in response to an active status or an inactive status of an j-th clock signal (where j is less than or equal to N) of the N clock signals. The first inverter receives the i-th data or the inverted i-th data from the logic section and inverts the i-th data or the inverted i-th data to output a first output signal. The output signal of the serializer may have reduced jitter even when the serializer operates in a high speed and a low power condition.

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