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21. 发明授权

US5970362A Simplified shallow trench isolation formation with no polish stop 失效
标题翻译：简化浅沟隔离结构，无抛光停止
公开(公告)号：US5970362A
公开(公告)日：1999-10-19
申请号：US992488
申请日：1997-12-18
申请人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
发明人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer, thereby simplifying the formation of the trench isolating structure, and enabling the substrate to be polished substantially flush with the trench fill. The planar trench fill-substrate interface avoids additional topography, thereby facilitating application of, and enhancing the accuracy of, photolithographic techniques in forming features with minimal dimensions.
摘要翻译：在省略了阻挡氮化物抛光停止层的半导体衬底中形成绝缘沟槽隔离结构，从而简化了沟槽隔离结构的形成，并使衬底能够与沟槽填充基本齐平。平面沟槽填充 - 衬底接口避免了额外的形貌，从而有助于光刻技术在最小尺寸形成特征时的应用和提高光刻技术的准确性。

22. 发明授权

US5953626A Dissolvable dielectric method 失效
标题翻译：溶解介电法
公开(公告)号：US5953626A
公开(公告)日：1999-09-14
申请号：US659166
申请日：1996-06-05
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

23. 发明授权

US5854515A Integrated circuit having conductors of enhanced cross-sectional area 失效
公开(公告)号：US5854515A
公开(公告)日：1998-12-29
申请号：US685143
申请日：1996-07-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

24. 发明授权

US5854131A Integrated circuit having horizontally and vertically offset interconnect lines 失效
标题翻译：集成电路具有水平和垂直偏移的互连线
公开(公告)号：US5854131A
公开(公告)日：1998-12-29
申请号：US655245
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H01L21/44
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

25. 发明授权

US5847462A Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 失效
标题翻译：集成电路具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US5847462A
公开(公告)日：1998-12-08
申请号：US748812
申请日：1996-11-14
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

26. 发明授权

US5827776A Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines 失效
标题翻译：制造集成电路的方法，其使用蚀刻停止件来产生交错的互连线
公开(公告)号：US5827776A
公开(公告)日：1998-10-27
申请号：US959106
申请日：1997-10-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/768 , H01L21/76816 , H01L23/5226 , H01L2924/0002
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.
摘要翻译：提供了多层互连结构。多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。三个导体中的两个导体在单独的垂直和水平平面中彼此交错。第三导体有利地在两个第二导体的至少一部分之间隔开横向距离。第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

27. 发明授权

US5783481A Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
标题翻译：具有用于产生气隙的聚酰亚胺的半导体层间电介质
公开(公告)号：US5783481A
公开(公告)日：1998-07-21
申请号：US659167
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L2924/0002
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.
摘要翻译：提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。介电沉积工艺优选包括两个沉积循环。使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

28. 发明授权

US06326298B1 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 有权
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US06326298B1
公开(公告)日：2001-12-04
申请号：US09513293
申请日：2000-02-25
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

29. 发明授权

US06309947B1 Method of manufacturing a semiconductor device with improved isolation region to active region topography 失效
标题翻译：制造具有改善的隔离区域到有源区域形貌的半导体器件的方法
公开(公告)号：US06309947B1
公开(公告)日：2001-10-30
申请号：US08944314
申请日：1997-10-06
申请人： Basab Bandyopadhyay , Douglas J. Bonser
发明人： Basab Bandyopadhyay , Douglas J. Bonser
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： A method of making a semiconductor device with improved isolation region to active region topography includes forming a masking layer on a surface of a substrate. A portion of the masking layer is removed to define one or more field regions and at least one trench is formed in the one or more field regions. An oxide layer is formed which substantially fills the trench and then a portion of the oxide layer is removed to leave the oxide layer with a relatively planar surface that is recessed with respect to the masking layer. The masking layer is then removed to expose the substrate. There may be a height differential between the substrate surface and the relatively planer surface of the oxide layer, however, the height differential is substantially less than the thickness of the masking layer.
摘要翻译：制造具有改善的隔离区域到有源区域形貌的半导体器件的方法包括在衬底的表面上形成掩模层。去除掩模层的一部分以限定一个或多个场区域，并且在一个或多个场区域中形成至少一个沟槽。形成氧化物层，其基本上填充沟槽，然后去除氧化物层的一部分以使氧化物层具有相对于掩模层凹陷的相对平坦的表面。然后去除掩模层以露出衬底。在衬底表面和氧化物层的相对平坦的表面之间可能存在高度差，然而，高差大大小于掩模层的厚度。

30. 发明授权

US6162699A Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery 有权
标题翻译：用于产生有限隔离沟槽宽度结构的方法和具有围绕其周边的窄隔离沟槽的器件
公开(公告)号：US6162699A
公开(公告)日：2000-12-19
申请号：US181561
申请日：1998-10-29
申请人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/945
摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.
摘要翻译：用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构区域层，多晶硅层和局部互连（LI）层。一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

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