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21. 发明授权

US06363111B1 Control loop for adaptive multilevel detection of a data signal 失效
标题翻译：用于数据信号自适应多电平检测的控制回路
公开(公告)号：US06363111B1
公开(公告)日：2002-03-26
申请号：US09076256
申请日：1998-05-12
申请人： Wong Hee , Abhijit Phanse
发明人： Wong Hee , Abhijit Phanse
IPC分类号： H04B346
CPC分类号： H04B17/327
摘要： A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.
摘要翻译：闭合反馈环路控制输入数据信号的切片或检测。处理关于输入数据信号的正峰值和负峰值的检测信号信息，以产生正和负峰值参考信号，其作为用于建立发生信号切片的阈值的参考信号电平。

22. 发明授权

US06301309B1 Signal gating controller for enhancing convergency of MLT3 data receivers 失效
标题翻译：信号门控控制器，用于增强MLT3数据接收器的收敛性
公开(公告)号：US06301309B1
公开(公告)日：2001-10-09
申请号：US09076425
申请日：1998-05-12
申请人： Wong Hee , Abhijit Phanse
发明人： Wong Hee , Abhijit Phanse
IPC分类号： H04L2534
CPC分类号： H04L25/03885 , H04L25/0292 , H04L25/061 , H04L25/4925
摘要： A signal gating controller for recovering true data signal pulses while gating out false data signal pulses which are generated and prevent convergence when recovering a multilevel data signal, such as an MLT3 Ethernet signal, which has been severely over-equalized. A signal slicing circuit generates two data peak signals: one data peak signal identifies occurrences of positive data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and positive peak signal levels; the other data peak signal identifies occurrences of negative data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and negative peak signal levels. A signal gating control circuit sequentially latches such data peak signals to produce two gating control signals. Logical combinations of such gating control and data peak signals produce gated signals in which the true data peak signal pulses remain while the false data peak signal pulses due to severe over-equalization of the incoming data signal are removed.
摘要翻译：一种信号选通控制器，用于在选择产生的伪数据信号脉冲时，恢复真实数据信号脉冲，并在恢复已经严重过度均衡的MLT3以太网信号等多级数据信号时防止收敛。信号分片电路产生两个数据峰值信号：一个数据峰值信号识别正数据信号峰值的出现，并且当输入数据信号电平已经转变到超过前一个零和正峰值信号电平之间的值时被断言; 另一个数据峰值信号识别负数据信号峰值的出现，并且当输入数据信号电平已经转变到超过前一个零和负峰值信号电平之间的值时被断言。信号门控控制电路顺序地锁存这样的数据峰值信号以产生两个选通控制信号。这种选通控制和数据峰值信号的逻辑组合产生门控信号，其中真实数据峰值信号脉冲保持，而由于输入数据信号的严重过均衡而导致的错误数据峰值信号脉冲被去除。

23. 发明授权

US6084466A Variable gain current summing circuit with mutually independent gain and biasing 有权
标题翻译：可变增益电流求和电路，具有相互独立的增益和偏置
公开(公告)号：US6084466A
公开(公告)日：2000-07-04
申请号：US176783
申请日：1998-10-22
申请人： Abhijit Phanse , Wong Hee
发明人： Abhijit Phanse , Wong Hee
IPC分类号： H03F3/00 , G06G7/12 , G08C13/00 , H03G3/30 , H04B3/36
CPC分类号： H03G3/001 , H03F3/45197 , H03G1/0029 , H04B3/04
摘要： A mixing circuit for combining biasing and signals using a selectively variable signal gain which is independent of the biasing and using biasing which is independent of the selectively variable signal gain. A Gilbert cell is used to multiply a differential control voltage, which represents a normalized signal gain factor, with input currents which include biasing components and input signal components. The resultant output current includes a bias component which is independent of the differential control voltage and a signal component which is independent of the input current biasing components. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage.
摘要翻译：一种混合电路，用于使用与选择性可变信号增益无关的偏置和使用偏置独立的选择性可变信号增益来组合偏置和信号。吉尔伯特单元用于将表示归一化信号增益因子的差分控制电压与包括偏置分量和输入信号分量的输入电流相乘。所得到的输出电流包括独立于差分控制电压的偏置分量和独立于输入电流偏置分量的信号分量。增益因子具有在零和单位之间的值，其相对于差分输入控制电压而变化。

24. 发明授权

US6044489A Data signal baseline error detector 失效
标题翻译：数据信号基准误差检测器
公开(公告)号：US6044489A
公开(公告)日：2000-03-28
申请号：US076261
申请日：1998-05-12
申请人： Wong Hee , Abhijit Phanse
发明人： Wong Hee , Abhijit Phanse
IPC分类号： G11B27/00 , H04L25/06
CPC分类号： H04L25/063
摘要： A data signal baseline error detector for monitoring and detecting undesired shifts in the baseline, or other intermediate level, of a multilevel data signal, such as an MLT3 Ethernet signal, as well as correcting for DC or low frequency offsets within a data receiving system. A signal slicing circuit generates two control signals: a data baseline signal indicates whether the data signal level is above or below a predetermined baseline reference level; and a data zero signal indicates when the data signal is in its zero, i.e., baseline, state and, when asserted, initiates a count sequence by a counter. The count sequence is decoded and the resulting decoded pulse sequence is gated in accordance with the data zero signal. Such pulses can be used to control a sampling circuit for sampling the data baseline signal or, alternatively, for sampling the data signal directly while in its zero state. The gating of the decoded pulses is done in such a manner as to prevent the outputting of decoded pulses which would otherwise occur too closely to the rising or falling edge of the data signal as it transitions away from its zero state, thereby ensuring that any signal sampling done occurs only during the true zero, or baseline, state of the data signal and not during any periods of signal level transitions.
摘要翻译：数据信号基准误差检测器，用于监测和检测诸如MLT3以太网信号的多电平数据信号的基线或其他中间电平中的不期望的移位，以及校正数据接收系统内的DC或低频偏移。信号分片电路产生两个控制信号：数据基线信号指示数据信号电平是否高于或低于预定的基线参考电平; 并且数据零信号指示数据信号何时为零，即基线状态，并且当被断言时，由计数器发起计数序列。对计数序列进行解码，并根据数据零信号对结果解码的脉冲序列进行门控。这样的脉冲可以用于控制采样电路以对数据基线信号进行采样，或者替代地，用于在处于零状态时直接采样数据信号。解码脉冲的门控以这样的方式完成，即防止输出解码的脉冲，否则当其从零状态转移时数据信号的上升沿或下降沿将太接近，从而确保任何信号采样完成仅在数据信号的真零或基线状态期间发生，而不是在信号电平转换的任何周期期间发生。

25. 发明授权

US08117249B1 Equalizer systems and methods utilizing analog delay elements 有权
标题翻译：使用模拟延迟元件的均衡器系统和方法
公开(公告)号：US08117249B1
公开(公告)日：2012-02-14
申请号：US11926869
申请日：2007-10-29
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee , Qian Yu , Abhijit Phanse
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee , Qian Yu , Abhijit Phanse
IPC分类号： G06F17/10
CPC分类号： H03F3/45183 , H03F2203/45634 , H03F2203/45638 , H03H11/265 , H03H15/02 , H04L2025/03477 , H04L2025/03617
摘要： Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade, such as for use within equalizers or other types of applications. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response over a wide frequency range while being tolerant of process variations. An equalizer, for example, may include the delay element within its feed forward filter and/or within its other circuits, such as within its adaptive coefficient generator or slicer input time-align circuit.
摘要翻译：系统和方法提供模拟延迟元件，其可以在隔离或级联中使用，例如用于均衡器或其他类型的应用中。例如，延迟元件可以包括宽带放大器和无源可编程滤波器，其可以在宽的频率范围内提供期望的幅度和组延迟响应，同时容忍工艺变化。例如，均衡器可以包括其前馈滤波器内和/或其其它电路内的延迟元件，例如在其自适应系数发生器或限幅器输入时间对准电路内。

26. 发明授权

US07561617B1 Channel monitoring and identification and performance monitoring in a flexible high speed signal processor engine 有权
标题翻译：在灵活的高速信号处理器引擎中进行信道监控和识别和性能监控
公开(公告)号：US07561617B1
公开(公告)日：2009-07-14
申请号：US11859649
申请日：2007-09-21
申请人： Abhijit G. Shanbhag , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Prashant Choudhary , Edem Ibragimov , Venugopal Balasubramonian , Qian Yu , Madabusi Govindarajan
发明人： Abhijit G. Shanbhag , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Prashant Choudhary , Edem Ibragimov , Venugopal Balasubramonian , Qian Yu , Madabusi Govindarajan
IPC分类号： H03H7/30
CPC分类号： H04L25/03063 , H04L25/03044 , H04L2025/03617
摘要： Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.
摘要翻译：公开了系统和方法来为通信信道提供信道监测和/或性能监测。例如，根据本发明的实施例，公开了一种对于信道失真进行均衡的均衡器，并且还提供信道和性能监视信息，例如带宽估计，信道识别，信噪比，色散，和/或偏振模色散。

27. 发明申请

US20070230557A1 ADAPTIVE SIGNAL EQUALIZER WITH ADAPTIVE ERROR TIMING AND PRECURSOR/POSTCURSOR CONFIGURATION CONTROL 有权
标题翻译：具有自适应错误时序的自适应信号均衡器和前端/ POSTAURSOR配置控制
公开(公告)号：US20070230557A1
公开(公告)日：2007-10-04
申请号：US11759720
申请日：2007-06-07
申请人： Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Qian Yu
发明人： Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Qian Yu
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H03H21/0012 , H03H2021/0096 , H04L7/0029 , H04L7/0062 , H04L7/0079 , H04L2025/0349 , H04L2025/03611
摘要： An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.
摘要翻译：一种具有前馈滤波器的自适应信号均衡器，其中反馈误差信号和相应的输入数据信号在时间上使用信号插值动态对准，此外，控制前驱/后沿滤波器抽头配置，由此产生更多的自适应滤波器抽头系数信号，显着改善和鲁棒的信号均衡。

28. 发明申请

US20060082406A1 CONSTRAINED COEFFICIENT ADAPTATION FOR CONTINUOUS-TIME EQUALIZERS 有权
标题翻译：对连续均衡器的约束系数适应
公开(公告)号：US20060082406A1
公开(公告)日：2006-04-20
申请号：US10970471
申请日：2004-10-20
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
IPC分类号： G06F7/44
CPC分类号： H04L25/03885
摘要： A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.
摘要翻译：提供了低压约束系数适应和乘法。为了提供约束系数自适应，加法器将自适应差分控制电压加到强制差分控制电压以提供有效系数。加法器被配置为使得强制差分控制电压可以防止自适应差分控制电压产生有效系数的符号变化。

29. 发明申请

US20060044167A1 Analog signal interpolation 有权
标题翻译：模拟信号插补
公开(公告)号：US20060044167A1
公开(公告)日：2006-03-02
申请号：US11209010
申请日：2005-08-22
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03M3/00
CPC分类号： G06G7/30 , H03F3/45183
摘要： A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
摘要翻译：提供了线性内插器，其包括被偏置的差分对晶体管，使得第一输入电压可以乘以因子r，其中0≤r≤1，并且使得第二输入电压可以乘以补码因子（1- r）。通过组合倍增的输入电压，基于因子r提供线性内插。

30. 发明申请

US20050271138A1 Adaptive signal latency control for communications systems signals 有权
公开(公告)号：US20050271138A1
公开(公告)日：2005-12-08
申请号：US11186241
申请日：2005-07-21
申请人： Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Edem Ibragimov , Fabian Giroud
发明人： Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit Shanbhag , Edem Ibragimov , Fabian Giroud
IPC分类号： H04L7/02 , H04L25/03 , H03H7/30
CPC分类号： H04L7/0062 , H04L7/0029 , H04L25/03057 , H04L2025/03503
摘要： An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

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