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11. 发明授权

US06511867B2 Utilizing atomic layer deposition for programmable device 有权
标题翻译：利用原子层沉积可编程器件
公开(公告)号：US06511867B2
公开(公告)日：2003-01-28
申请号：US09896529
申请日：2001-06-30
申请人： Tyler A. Lowrey , Charles H. Dennison
发明人： Tyler A. Lowrey , Charles H. Dennison
IPC分类号： H01L2182
CPC分类号： H01L21/7685 , H01L21/28562 , H01L21/76888 , H01L27/24
摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.
摘要翻译：在一方面，提供一种设置和重新编程可编程设备的状态的设备。在一方面，提供了一种方法，使得通过暴露接触的电介质形成开口，接触形成在基底上。利用原子层沉积（ALD）将电极保形地沉积在电介质的壁上。可编程材料形成在电极上，导体形成可编程材料。在一个方面，在电极和可编程材料之间利用ALD共形沉积屏障。

12. 发明授权

US06429031B2 Method for forming wiring pattern of a semiconductor integrated circuit 失效
标题翻译：用于形成半导体集成电路的布线图案的方法
公开(公告)号：US06429031B2
公开(公告)日：2002-08-06
申请号：US09725268
申请日：2000-11-29
申请人： Makoto Yamada , Mitsuo Ito
发明人： Makoto Yamada , Mitsuo Ito
IPC分类号： H01L2182
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for connecting wiring patterns of an integrated circuit device. A wiring pattern of a semiconductor integrated circuit includes a first line for conducting a first potential and a second line for conducting a second potential. The method detects a portion of a distal end of the first line that overlaps a distal end of the second line and generates an avoidance pattern by eliminating the overlapping portion from the first line.
摘要翻译：一种用于连接集成电路装置的布线图案的方法和装置。半导体集成电路的布线图形包括用于导通第一电位的第一线和用于导通第二电位的第二线。该方法检测与第二线的远端重叠的第一线的远端的一部分，并通过消除与第一线重叠的部分来产生回避模式。

13. 发明授权

US06426243B1 Methods of forming dynamic random access memory circuitry 有权
标题翻译：形成动态随机存取存储器电路的方法
公开(公告)号：US06426243B1
公开(公告)日：2002-07-30
申请号：US09810586
申请日：2001-03-15
申请人： Belford T. Coursey
发明人： Belford T. Coursey
IPC分类号： H01L2182
CPC分类号： H01L27/10855 , H01L27/10894 , H01L28/90
摘要： A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least, one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.
摘要翻译：一种形成具有存储器阵列的存储器电路的方法，所述存储器阵列具有多个存储电容器并且具有可操作地配置为写入存储器阵列和从存储器阵列读取的外围存储器电路，包括在半导体衬底上形成电介质阱形成层去除井形成层的一部分有效地在井形成层内形成至少一个井。存储单元电容器阵列形成在阱内。外围存储器电路形成在井形成层存储器阵列的横向外侧。在一个实现中，存储器电路包括半导体衬底。多个字线被接收在半导体衬底上。在字线和衬底上接收绝缘层。至少绝缘层至少形成一个。井底有一个接收字母的基地。外围界面定义了存储器阵列区域的轮廓。井的外围区域包括存储器外围电路区域。多个存储单元存储电容器被接收在该字符串内的阱内。在外围电路区域内接收外围电路，并且可操作地配置为写入存储器阵列并从存储器阵列读取。

14. 发明授权

US06403403B1 Diode isolated thin film fuel cell array addressing method 有权
标题翻译：二极管隔离薄膜燃料电池阵列寻址方法
公开(公告)号：US06403403B1
公开(公告)日：2002-06-11
申请号：US09660135
申请日：2000-09-12
申请人： Donald C. Mayer , Jon V. Osborn , Siegfried W. Janson , Peter D. Fuqua
发明人： Donald C. Mayer , Jon V. Osborn , Siegfried W. Janson , Peter D. Fuqua
IPC分类号： H01L2182
CPC分类号： H01L27/10 , F02K9/95
摘要： The method addresses and interrogates addressable cells having at least one element including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to un addressed elements, for selectively addressing one of the cells using row and column address line in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heating element can be used for igniting a respective fuel cell in an array of fuel cells disposed in a thin film microthruster. After ignition, the address lines are used to interrogate the cell location for verification of fuel cell ignition well suited for monitoring fuel burns and usage of the microthruster.
摘要翻译：该方法寻址和询问具有至少一个元件的可寻址单元，其包括用作加热元件的多晶硅电阻器和阻塞二极管，以防止潜在的未被寻址元件的潜入电流，用于使用薄膜结构中的行和列地址线来选择性地寻址单元中的一个单元具有最小数量的地址线和最小层数。电阻加热元件可以用于点燃设置在薄膜微推力器中的燃料电池阵列中的相应燃料电池。点火后，地址线用于询问电池位置，以验证燃料电池点火，非常适合监控燃料燃烧和微型推进器的使用。

15. 发明授权

US06368902B1 Enhanced efuses by the local degradation of the fuse link 失效
标题翻译：通过熔断器局部劣化增强了电流
公开(公告)号：US06368902B1
公开(公告)日：2002-04-09
申请号：US09580132
申请日：2000-05-30
申请人： Chandrasekharan Kothandaraman , Frank Grellner , Sundar Kumar Iyer
发明人： Chandrasekharan Kothandaraman , Frank Grellner , Sundar Kumar Iyer
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable “blowing” of the fuse in the fuse region underlying the filler material. Since the “blow” area is predictable, damage to adjacent structures can be minimized or eliminated.
摘要翻译：这里描述的是一种保险丝，其包括设置在多晶硅层上的导电层上的覆盖层。覆盖层优选地包括相对惰性的材料，例如氮化物蚀刻剂屏障。覆盖层优选具有相对较少惰性填料的区域。在对熔丝进行编程时，可以是硅化物的导电层优选在覆盖层的填充材料下方的区域中降解。这种优先的劣化导致在填充材料下面的保险丝区域中的可预见的“熔断”熔丝。由于“打击”区域是可预测的，所以可以最小化或消除对相邻结构的损坏。

16. 发明授权

US06362024B1 Semiconductor memory device manufacturing method with fuse cutting performance improved 有权
标题翻译：具有保险丝切割性能的半导体存储器件制造方法得到改进
公开(公告)号：US06362024B1
公开(公告)日：2002-03-26
申请号：US09440464
申请日：1999-11-15
申请人： Makoto Kotou , Shinya Iwasa
发明人： Makoto Kotou , Shinya Iwasa
IPC分类号： H01L2182
CPC分类号： H01L27/10894 , H01L23/5258 , H01L27/10814 , H01L27/10852 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor memory device, a first interlayer insulating film is formed to have at least one fuse therein. An etching stopper film is formed on the first interlayer insulating film. A first layer is formed on the etching stopper film. The first layer is etched to the etching stopper film using a first mask. Then, the etching stopper film is etched to produce a fuse cutting window.
摘要翻译：在制造半导体存储器件的方法中，形成第一层间绝缘膜以在其中具有至少一个熔丝。在第一层间绝缘膜上形成蚀刻停止膜。在蚀刻停止膜上形成第一层。使用第一掩模将第一层蚀刻到蚀刻停止膜。然后，蚀刻停止膜被蚀刻以产生熔丝切割窗。

17. 发明授权

US06335228B1 Method for making an anti-fuse 有权
标题翻译：制造防熔丝的方法
公开(公告)号：US06335228B1
公开(公告)日：2002-01-01
申请号：US09476726
申请日：1999-12-30
申请人： Robert T. Fuller , Frank Prein
发明人： Robert T. Fuller , Frank Prein
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact (20) and a normal (i.e. non-fused) contact (10) are formed by opening respective contact areas in a dielectric (110), selectively forming an insulating layer (210) over the anti-fuse contact, applying polysilicon (212, 410) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation (810) to improve its conductivity before the anti-fuse contact is formed. In another embodiment of the invention, the anti-fuse is formed in an isolated well (1212) on the integrated circuit device and a non-fused contact (1216) to the well is also provided to aid in blowing the anti-fuse.
摘要翻译：用于产生具有冗余部件的动态随机存取存储器（DRAM）的制造方法包括用于同时向DRAM的组件和与多个组件的抗熔接触部形成正常（即非熔接）触点的步骤。使用标准集成电路处理技术容易地实现正常和防熔接触点的制造过程。通过在电介质（110）中打开相应的接触区域，在反熔丝接触件上选择性地形成绝缘层（210）来形成反熔丝接触件（20）和法线（即未熔接的）接触件（10）施加多晶硅（212,410）以覆盖抗熔丝接触的绝缘层并填充正常触点上的开口。在本发明的一个实施例中，由抗熔丝接触所服务的电路区域经受离子注入（810）以在形成抗熔丝接触之前提高其导电性。在本发明的另一个实施例中，反熔丝形成在集成电路器件上的隔离阱（1212）中，并且还提供了与阱的非熔断接触（1216）以帮助吹入反熔丝。

18. 发明授权

US06319758B1 Redundancy structure in self-aligned contact process 有权
公开(公告)号：US06319758B1
公开(公告)日：2001-11-20
申请号：US09329783
申请日：1999-06-10
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy structure has a fusible link formed of a layer of a conductive material deposited upon an insulating layer such as field oxide on the semiconductor substrate and connected between the redundant circuits and other circuits present on the integrated circuit. The layer of conductive material is either formed of a metal such as Aluminum or Tungsten, a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten and a heavily doped polycrystalline silicon. A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit. The hard mask layer is removed from the layer of conductive layer for deposition of interlayer dielectric layers on the semiconductor substrate to improve a fuse destruction to implement the redundant circuits. An opening is formed in the interlayer dielectric layers to thin the interlayer dielectric layers to allow exposure of the layer of conductive material to facilitate destruction of the layer of conductive material.

19. 发明授权

US06255141B1 Method of packaging fuses 有权
标题翻译：包装保险丝的方法
公开(公告)号：US06255141B1
公开(公告)日：2001-07-03
申请号：US09391137
申请日：1999-09-07
申请人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
发明人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
IPC分类号： H01L2182
CPC分类号： H01L23/62 , H01L2224/13
摘要： Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
摘要翻译：描述了与集成电路器件一起封装外部保险丝的改进方法。提供了一对框带，每个框带具有一组相关的接触垫。将电阻浆料施加到接触垫组中的一个，并且通过固化位于接触垫组之间的电阻浆料将框带层压在一起。骰子安装到第二接触焊盘的相对侧，以形成具有整体封装的外部熔断器的集成电路器件。封装的装置最终被单独使用。在一些实施例中，接触垫每个都具有在每个管芯的相对侧上形成翅膀的下降的突片。当芯片是倒装芯片时，可以通过将裸片上的凸起和凸片翼尖焊接到基板来将装置附接到基板。在优选实施例中，电阻膏是正温度系数电阻膏。

20. 发明授权

US06238955B1 Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry 有权
标题翻译：集成电路熔断器形成方法，集成电路编程方法和相关集成电路
公开(公告)号：US06238955B1
公开(公告)日：2001-05-29
申请号：US09135377
申请日：1998-08-17
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided. The programming circuitry comprises at least one MOS device which is capable of being utilized to provide a programming voltage which is sufficient to blow the fuse, and which is no greater than the breakdown voltage of the one MOS device.
摘要翻译：描述了集成电路熔丝形成方法，集成电路编程方法和相关的集成电路。在一个实施方案中，在衬底上形成包括第一导电材料的第一层。包含不同于第一导电材料的第二导电材料的第二层形成在第一层上并与其导电连接。通过去除第一层和第二层中的一个的至少一部分形成保险丝区域。在优选的方面，提供了包括设置在两个导电层之间的一层的层的组件。从两层之间移除一层的至少一部分以在它们之间形成空隙。在另一方面，在衬底上提供编程电路，在衬底上提供了层的组合。编程电路包括至少一个MOS器件，其能够用于提供足以熔断熔丝的编程电压，其不大于一个MOS器件的击穿电压。

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