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11. 发明授权

US4276649A Receiver for digital signals in line code 失效
标题翻译：接收机用于线路码中的数字信号
公开(公告)号：US4276649A
公开(公告)日：1981-06-30
申请号：US50712
申请日：1979-06-21
申请人： Gradus C. Groenendaal , Einar A. Aagaard
发明人： Gradus C. Groenendaal , Einar A. Aagaard
IPC分类号： H03M5/12 , H04B14/04 , H04B14/06 , H04L1/24 , H04L25/49 , G06F11/00
CPC分类号： H04L25/49 , H04B14/06 , H04L1/245
摘要： Receiver for a digital line code signal. This receiver comprises a line code decoder and a digital-to-analog converter. To reduce the audibility of bursts this receiver also comprises a line-code violation detector detecting whether the received signal deviates from the line code; as well as a pulse generator. Each time the line-code violation detector detects that the received signal deviates from the line code, the output signal of the pulse generator is applied to the digital-to-analog converter instead of the output signal of the line code decoder.
摘要翻译：接收机用于数字线路码信号。该接收机包括线路码解码器和数模转换器。为了降低突发的可听性，该接收机还包括检测接收到的信号是否偏离行码的行代码违规检测器; 以及脉冲发生器。每当行代码违规检测器检测到接收到的信号偏离行代码时，脉冲发生器的输出信号被施加到数模转换器而不是行代码解码器的输出信号。

12. 发明申请

US20180248571A1 FULLY INTEGRATED POWER AMPLIFIER EMPLOYING TRANSFORMER COMBINER WITH ENHANCED BACK-OFF EFFICIENCY 审中-公开
公开(公告)号：US20180248571A1
公开(公告)日：2018-08-30
申请号：US15798304
申请日：2017-10-30
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Hongrui WANG , Ali AFSAHI , Vikram MAGOON
IPC分类号： H04B1/04 , H04B7/005 , H03G3/30 , H04B14/06 , H04B1/00 , H05K13/04
CPC分类号： H04B1/04 , H03G3/3042 , H04B1/0017 , H04B7/005 , H04B14/06 , H04B2001/0416 , H05K13/046 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/40 , Y02D70/44
摘要： A fully integrated power amplifier (PA) employing a transformer combiner with enhanced back-off efficiency includes a first PA to amplify a first radio frequency (RF) signal and a second PA to amplify a second RF signal. A first variable capacitor is coupled between differential output nodes of the first PA. A second variable capacitor is coupled between differential output nodes of the second PA. The differential outputs of the first PA and the second PA are coupled via respective first and second transformers to a load. Capacitance values associated with the first and second variable capacitors are dynamically adjustable based on an amplitude of the RF signal to achieve a desired power efficiency at an output power level.

13. 发明申请

US20160374538A1 ELECTRONIC ENDOSCOPE 审中-公开
标题翻译：电子内窥镜
公开(公告)号：US20160374538A1
公开(公告)日：2016-12-29
申请号：US15262042
申请日：2016-09-12
申请人： OLYMPUS CORPORATION
发明人： Takahiro TANABE , Koji SAKUMA
IPC分类号： A61B1/00 , A61B1/05
CPC分类号： A61B1/00114 , A61B1/00009 , A61B1/00018 , A61B1/00124 , A61B1/00186 , A61B1/05 , H04B14/06
摘要： An electronic endoscope transmits an image pickup signal converted into digital serial data, as a differential signal, to a processor such that a quality of an output waveform to the processor is fixed, and includes: a first transmission section; a first filter section arranged at an output side of the first transmission section, wherein a constant is adjusted according to a loss in a transmission channel including a cable disposed in a part from the first transmission section to the first filter section; a second transmission section for transmitting the differential signal from the first filter section to the processor; and a second filter section arranged at an output side of the second transmission section, wherein a constant is adjusted according to a loss including a cable located in the second transmission section or in a portion subsequent to the second transmission section.
摘要翻译：电子内窥镜将转换成数字串行数据的图像拾取信号作为差分信号发送到处理器，使得对处理器的输出波形的质量固定，并且包括：第一发送部分; 布置在第一传输部分的输出侧的第一滤波器部分，其中根据包括设置在从第一传输部分到第一过滤部分的部分中的电缆的传输通道的损耗来调节常数; 第二传输部分，用于将来自第一滤波器部分的差分信号传送到处理器; 以及布置在所述第二传输部分的输出侧的第二过滤器部分，其中根据包括位于所述第二传动部分中的缆索或所述第二传动部分之后的部分的损失来调整常数。

14. 发明申请

US20160337979A1 POWER EFFICIENT, VARIABLE SAMPLING RATE DELTA-SIGMA DATA CONVERTERS FOR FLEXIBLE RADIO COMMUNICATION SYSTEMS 有权
标题翻译：功率有效，灵活的无线电通信系统的可变采样率DELTA-SIGMA数据转换器
公开(公告)号：US20160337979A1
公开(公告)日：2016-11-17
申请号：US15103306
申请日：2015-11-06
申请人： GM GLOBAL TECHNOLOGY OPERATIONS LLC
发明人： TIMOTHY J. TALTY , CYNTHIA D. BARINGER , MOHIUDDIN AHMED , ALBERT E. COSAND , JAMES CHINGWEI LI , PETER PETRE , ZHIWEI A. XU , YEN-CHENG KUAN
IPC分类号： H04W52/02 , H04B1/3822 , H04B1/40
CPC分类号： H04W52/0261 , H04B1/0007 , H04B1/0057 , H04B1/0483 , H04B1/18 , H04B1/3822 , H04B1/40 , H04B1/52 , H04B14/06 , H04W52/0274 , Y02D70/00 , Y02D70/1224 , Y02D70/1262 , Y02D70/142 , Y02D70/164 , Y02D70/40
摘要： A method for reducing power consumption in a transceiver front-end circuit for a cellular radio. The transceiver circuit includes a receiver module having a delta-sigma modulator that converts analog receive signals to a representative digital signal in an interleaving process, where the delta-sigma modulator includes a low noise amplifier (LNA), an LC filter and a quantizer circuit. The LC filter is a multi-order filter and the quantizer circuit is an interleaving quantizer circuit that interleaves multiple groups of bits from the filter. The method includes selectively reducing the order of the LC filter in situations where a full dynamic range of the cellular radio is not required and reducing a bit resolution of the quantizer circuit so as to reduce the power requirements of the cellular radio.
摘要翻译：一种用于降低用于蜂窝无线电的收发器前端电路中的功率消耗的方法。收发器电路包括具有Δ-Σ调制器的接收器模块，其在交错过程中将模拟接收信号转换为代表性数字信号，其中Δ-Σ调制器包括低噪声放大器（LNA），LC滤波器和量化器电路。 LC滤波器是多阶滤波器，量化器电路是从滤波器交织多组位的交错量化器电路。该方法包括在不需要蜂窝无线电的全动态范围的情况下选择性地降低LC滤波器的次序，并降低量化器电路的位分辨率，从而降低蜂窝无线电的功率需求。

15. 发明授权

US08433024B2 Spread spectrum clock generator and method for adjusting spread amount 有权
标题翻译：扩频时钟发生器和调整扩展量的方法
公开(公告)号：US08433024B2
公开(公告)日：2013-04-30
申请号：US12693520
申请日：2010-01-26
申请人： Chia-Tseng Chiang , Hen-Wai Tsao
发明人： Chia-Tseng Chiang , Hen-Wai Tsao
IPC分类号： H03D3/24
CPC分类号： H04B14/06 , H04B1/69
摘要： A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.
摘要翻译：扩频时钟发生器包括三角形调制器，ΔΣ调制器，分频器和锁相环。三角形调制器根据数字并行信号产生代表十进制的数字调制信号，其中扩展量与数字并行信号成比例。电连接到三角形调制器的Δ-Σ调制器根据数字调制信号产生包括十进制和整数的除数除数。分频器根据除法器除法器分频输出信号时钟的频率以产生分频时钟信号，其中分频时钟信号的频率基本上等于通过将输出时钟信号的频率除以除数除数。锁相环根据分频时钟信号和参考时钟信号调节输出时钟信号的频率。

16. 发明授权

US07643579B2 Multiple differential demodulator using weighting value 失效
标题翻译：多重差分解调器采用加权值
公开(公告)号：US07643579B2
公开(公告)日：2010-01-05
申请号：US11457116
申请日：2006-07-12
申请人： Sang Hyun Min , Tah Joon Park , U Sang Lee , Koon Shik Cho , Kwang Mook Lee
发明人： Sang Hyun Min , Tah Joon Park , U Sang Lee , Koon Shik Cho , Kwang Mook Lee
IPC分类号： H04L27/22 , H03D3/22 , H04L27/06
CPC分类号： H04B14/06 , H04W84/10
摘要： The present invention relates to a multiple differential demodulator using a weighting value. The multiple differential demodulator according to the present invention includes a weighting value generator for integrating a real part and an imaginary part of a value acquired by multiplying one of a plurality of differentiated reception signals by a conjugated value of a differentiated PN code signal corresponding to a preset symbol, and determining the greater of the integrated real and integrated imaginary parts to apply a predetermined weighting value to the greater value, where the PN code signal is differentiated in the same fashion as the differentiated reception signals.
摘要翻译：本发明涉及使用加权值的多重差分解调器。根据本发明的多重差分解调器包括一个加权值产生器，用于将通过将多个差分接收信号中的一个相乘而得到的值的实部和虚部进行积分，该复数值与对应于并且确定积分的实数和积分虚部中的较大者，以将预定加权值应用于较大值，其中PN码信号以与差分接收信号相同的方式进行微分。

17. 发明申请

US20030210746A1 Radio transmission frequency digital signal generation 有权
标题翻译：无线电传输频率数字信号产生
公开(公告)号：US20030210746A1
公开(公告)日：2003-11-13
申请号：US10392290
申请日：2003-03-19
申请人： The Regents of the University of California
发明人： Peter M. Asbeck , Ian Galton
IPC分类号： H04B014/06
CPC分类号： H04B14/06
摘要： The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.
摘要翻译：本发明涉及RF信号的数字生成。在数字领域，数字RF信号被转换成与RF载波相位同步的高速时钟时钟的数字信号。带通Δ-Σ调制器从转换的数字信号产生位流。

18. 发明授权

US06639946B2 Sigma delta modulator with SAW filter 有权
公开(公告)号：US06639946B2
公开(公告)日：2003-10-28
申请号：US09726421
申请日：2000-12-01
申请人： Miaochen Wu , Aria Eshraghi , Theodore Tewksbury
发明人： Miaochen Wu , Aria Eshraghi , Theodore Tewksbury
IPC分类号： H04B1406
CPC分类号： H04B14/06 , H03M3/404 , H03M3/43 , H03M3/456
摘要： A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

19. 发明授权

US06549580B1 Subset averaged median predictor for differential pulse code modulation 失效
标题翻译：差分脉冲编码调制的子集平均中值预测器
公开(公告)号：US06549580B1
公开(公告)日：2003-04-15
申请号：US09255632
申请日：1999-02-22
申请人： Dong-hee Kang
发明人： Dong-hee Kang
IPC分类号： H04B1406
CPC分类号： H04B14/06
摘要： A predictor for differential pulse code modulation that designates a subset averaged median (SAM) predictor, which removes transmission errors and/or minimizes error propagation. The SAM predictor in a preferred embodiment operates according to SAM ⁢ ⁢ ( X ) = ∑ i = 1 P ⁢ ⁢ a i ⁢ F i ⁢ ( X ) where X is an input vector within a predictor window, P is the number of median subfilters, ai is an optionally selected coefficient and Fi( ) is a feature equation of an ith median subfilter. The coefficients ai may be selected so as to minimize a prediction error variance and to exclude first order subfilters, where ∑ i = l P ⁢ ⁢ &LeftBracketingBar; a i &RightBracketingBar;
摘要翻译：用于差分脉冲编码调制的预测器，其指定子集平均中值（SAM）预测器，其消除传输误差和/或最小化误差传播。优选实施例中的SAM预测器根据其中X是在预测器窗口内的输入向量进行操作，P是中值子滤波器的数量，ai是可选择的系数，Fi（）是第i个中间子滤波器的特征方程。可以选择系数ai以最小化预测误差方差，并排除一级子滤波器，其中通过最小化误差传播来消除传输误差并最小化预测误差方差。

20. 发明申请

US20020158784A1 WIRELESS LOCAL LOOP TERMINAL AND SYSTEM HAVING HIGH SPEED, HIGH RESOLUTION, DIGITAL-TO ANALOG CONVERTER WITH OFF-LINE SIGMA DELTA CONVERSION AND STORAGE 有权
标题翻译：无线本地环路终端和具有高速，高分辨率，数字模拟转换器的离线SIGMA DELTA转换和存储的系统
公开(公告)号：US20020158784A1
公开(公告)日：2002-10-31
申请号：US09846440
申请日：2001-04-30
发明人： Carl M. Panasik , T. R. Viswanathan
IPC分类号： H03M001/66 , H03M003/00
CPC分类号： H04B14/06 , H03M3/50
摘要： A wireless local loop apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a wireless local loop terminal (302) and corresponding system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.
摘要翻译：一种无线本地环路装置和相应的系统，其具有可以以比以前可实现的更高的速度工作的改进的DAC，其以不同的方式利用了Σ-Δ原理。更具体地说，本发明包括实现数模转换电路（105）的无线本地环路终端（302）和对应系统（300），数字 - 模拟转换电路（105）包括诸如只读存储器的存储装置（110）对应于耦合到多个一位数模转换器（120,122,124,126）的数字输入（106）的所有可能值的Δ-Σ模拟序列。每个数模转换器（120,122,124,126）由多相时钟计时，使得施加到数模转换器（120,122,124,126中的每一个）的每个相位）在过采样期间相对于彼此延迟。加法器耦合到每个数模转换器（120,122,124,126），用于对来自每个数模转换器（120,122,124,126）的每个输出求和以产生模拟输出。因此，根据本发明的数模转换电路（105）模拟具有高速和高分辨率的三角形数模转换器。

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