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11. 发明授权

US5574452A Single bit bandpass analog-to-digital converter 失效
标题翻译：单位带通模拟数字转换器
公开(公告)号：US5574452A
公开(公告)日：1996-11-12
申请号：US196354
申请日：1994-02-15
申请人： Lorenzo L. Longo , Raouf Halim , Bor-Rong Horng
发明人： Lorenzo L. Longo , Raouf Halim , Bor-Rong Horng
IPC分类号： H03M3/02
CPC分类号： H03M3/324 , H03M3/406 , H03M3/43 , H03M3/454
摘要： A single bit bandpass analog-to-digital converter has an analog summer, an analog bandpass filter, a single bit quantizer, and a single bit digital-to-analog converter connected in a loop. An input signal to the single bit filter is applied to a plus input terminal of the summer, and the output of the digital-to-analog converter is applied to a minus input terminal of the summer. The output signal from the single bit filter is taken from the output of the quantizer. The bandpass filter is preferably driven by a digital clock running at the same frequency as the quantizer and the digital-to-analog converter. This architecture reduces quantization noise within the passband at the possible expense of increasing it outside the passband. The passband is centered precisely on one-quarter of the clock frequency.
摘要翻译：单位带通模拟数字转换器具有模拟加法器，模拟带通滤波器，单比特量化器和以循环连接的单比特数模转换器。将单位滤波器的输入信号施加到加法器的正输入端，并且数模转换器的输出被施加到夏季的负输入端。来自单位滤波器的输出信号取自量化器的输出。带通滤波器优选地以与量化器和数模转换器相同的频率运行的数字时钟驱动。这种架构降低了通带内的量化噪声，可能会增加通带外的噪声。通带正好位于时钟频率的四分之一。

12. 发明授权

US5113189A Frequency translating coherent analog to digital conversion system for modulated signals 失效
标题翻译：用于调制信号的频率转换相干模数转换系统
公开(公告)号：US5113189A
公开(公告)日：1992-05-12
申请号：US718891
申请日：1991-06-21
申请人： Dion D. Messer , Sangil Park , Charles D. Thompson
发明人： Dion D. Messer , Sangil Park , Charles D. Thompson
IPC分类号： H03M1/12 , H03M3/00 , H03M3/02 , H04B1/16 , H04B14/06
CPC分类号： H03M3/324 , H03M3/37 , H03M3/458
摘要： A analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), and A/D converter (18), an oscillator (12) and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.
摘要翻译：模数（A / D）转换系统（10或20）接收调制的模拟信号，将信号的频率转换为较低的频率，并将模拟信号转换成滤波的数字信号。在一种形式中，转换系统（10）具有模拟信号乘法器（16）和A / D转换器（18），振荡器（12）和分频器（14）。倍频器（16）转换模拟信号的频率，A / D转换器（18）将模拟信号转换为数字形式。分频器（14）从振荡器（12）接收时钟信号，并分频时钟信号的频率。由于相同的时钟信号用于频率转换和模数转换，所以在输出数字信号中不会引入相位误差。此外，分频器（14）迫使模拟和数字信号的频率成为后续解调的整数比。

13. 发明授权

US12126363B2 Error cancellation delta-sigma DAC with an inverting amplifier-based filter 有权
公开(公告)号：US12126363B2
公开(公告)日：2024-10-22
申请号：US17876679
申请日：2022-07-29
申请人： Cisco Technology, Inc.
发明人： Bibhu Prasad Das , Romesh Kumar Nandwana , Richard Van Hoesen Booth , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/50
摘要： An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.

14. 发明授权

US09692446B2 Delta-Sigma ADC with wait-for-sync feature 有权
公开(公告)号：US09692446B2
公开(公告)日：2017-06-27
申请号：US15281354
申请日：2016-09-30
申请人： Texas Instruments Incorporated
发明人： Robert James Landers
IPC分类号： H03M3/00 , G06F13/24 , G06F13/16
CPC分类号： H03M3/462 , G06F13/1673 , G06F13/1689 , G06F13/24 , H03M3/324
摘要： An integrated circuit (IC) chip containing a Delta-Sigma (ΔΣ) filter module for a ΔΣ analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ΔΣ filter that is connected to receive a digital data stream created by a ΔΣ modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

15. 发明授权

US09590654B2 Signal modulation circuit 有权
标题翻译：信号调制电路
公开(公告)号：US09590654B2
公开(公告)日：2017-03-07
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
发明人： Yoshinori Nakanishi , Tsuyoshi Kawaguchi , Mamoru Sekiya
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/348 , H03M3/358 , H03M3/42
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译：提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈用于将驱动信号从驱动电路反馈到输入信号的电路。

16. 发明申请

US20150222289A1 SIGMA-DELTA MODULATOR AND ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译： SIGMA-DELTA调制器和模拟数字转换器
公开(公告)号：US20150222289A1
公开(公告)日：2015-08-06
申请号：US14425095
申请日：2013-02-28
申请人： INSTITUTE OF MICROELECTRINICS, CHINESE ACADEMY OF SCIENCES
发明人： Lan Chen
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/324 , H03M1/002 , H03M3/38 , H03M3/424 , H03M3/438 , H03M3/50
摘要： A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator.
摘要翻译： Σ-Δ调制器和模数转换器。 Sigma-Delta调制器包括量化器，校正模块和RC积分器。校正模块包括产生校正水平的预定电阻。校正模块用于通过使用量化器中的比较器将校正电平与预定参考电压进行比较，以产生数字校正信号，基于该校正信号校正RC积分器中的电阻校正阵列中的电阻。预定电阻与RC积分器中的电阻校正阵列中的电阻相同。 Sigma-Delta调制器和模数转换器可以校正RC积分器中的电阻偏差。

17. 发明申请

US20150207519A1 SIGNAL MODULATION CIRCUIT 有权
标题翻译：信号调制电路
公开(公告)号：US20150207519A1
公开(公告)日：2015-07-23
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
发明人： Yoshinori NAKANISHI , Tsuyoshi KAWAGUCHI , Mamoru SEKIYA
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/348 , H03M3/358 , H03M3/42
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译：提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈用于将驱动信号从驱动电路反馈到输入信号的电路。

18. 发明授权

US07619549B2 Methods and systems for reducing a sign-bit pulse at a voltage output of a sigma-delta digital-to-analog converter 有权
标题翻译：用于减小Σ-Δ数模转换器的电压输出处的符号位脉冲的方法和系统
公开(公告)号：US07619549B2
公开(公告)日：2009-11-17
申请号：US11874737
申请日：2007-10-18
申请人： Paul M. Werking
发明人： Paul M. Werking
IPC分类号： H03M3/00
CPC分类号： H03M3/324 , H03M3/376 , H03M3/50
摘要： For a sigma-delta digital-to-analog converter (SD DAC) that includes a voltage output and a low-pass filter having a given order, methods and systems for reducing a sign-bit pulse at the voltage output of the SD DAC without requiring use of a higher order low-pass filter are disclosed. A method includes receiving a first waveform and a second waveform, the first and second waveforms having a first phase relationship; setting the first phase relationship between the first and second waveforms to a second phase relationship by aligning at least one of the first and second waveforms such that a transition of the second waveform is approximately half way between a rising edge and adjacent falling edge of the first waveform; upon setting the second phase relationship, multiplying the first and second waveforms to produce a digital input; and providing the digital input to the SD DAC.
摘要翻译：对于包含电压输出和给定顺序的低通滤波器的Σ-Δ数模转换器（SD DAC），用于减少SD DAC电压输出时的符号位脉冲的方法和系统，无需需要使用高阶低通滤波器。一种方法包括：接收第一波形和第二波形，所述第一和第二波形具有第一相位关系; 将第一和第二波形之间的第一相位关系设置为第二相位关系，通过对准第一和第二波形中的至少一个，使得第二波形的转变大约是第一波形的上升沿和相邻下降沿之间的一半波形; 在设置第二相位关系时，将第一和第二波形相乘以产生数字输入; 并向SD DAC提供数字输入。

19. 发明授权

US07557744B2 PWM driver and class D amplifier using same 有权
标题翻译： PWM驱动器和D类放大器使用相同
公开(公告)号：US07557744B2
公开(公告)日：2009-07-07
申请号：US11263453
申请日：2005-10-31
申请人： Toru Ido , Soichiro Ishizuka
发明人： Toru Ido , Soichiro Ishizuka
IPC分类号： H03M1/82
CPC分类号： H03F3/217 , H03F2200/331 , H03M3/324 , H03M3/432 , H03M3/456 , H03M3/50
摘要： The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.
摘要翻译：本发明的目的是提供一种可以减少混叠噪声的D类放大器。 D类放大器具有以第一采样频率工作的D / A转换器10和接收D / A转换器10的输出的PWM驱动器3.所述PWM驱动器3以与第一采样频率同步的第二采样频率工作。第二采样频率可以与PWM驱动器的增量波频率相关。此外，所述第一采样频率和所述第二采样频率的同步可以执行，其中一个频率是另一个的整数倍。

20. 发明申请

US20080316075A1 DELTA SIGMA MODULATOR AND DELTA SIGMA A/D CONVERTER 有权
标题翻译： DELTA SIGMA调制器和DELTA SIGMA A / D转换器
公开(公告)号：US20080316075A1
公开(公告)日：2008-12-25
申请号：US12143331
申请日：2008-06-20
申请人： Kazuo HASEGAWA
发明人： Kazuo HASEGAWA
IPC分类号： H03M3/02
CPC分类号： G06F1/06 , H03M3/324 , H03M3/458
摘要： With a delta sigma modulator of this invention, a plurality of clocks required to control a switching circuit can be easily generated and correlation among phases of the plurality of clocks can be automatically maintained while a frequency of the clocks is modified. A ring oscillator is formed of three delay circuits provided with differential amplifiers in the delta sigma modulator. A clock producing circuit produces the plurality of clocks to control the switching circuit by delaying three-phase clocks outputted from the ring oscillator. All the tail currents Ic in the differential amplifiers in the delay circuits in the ring oscillator and the tail currents Ic in the differential amplifiers in the delay circuits in the clock producing circuit are proportional to each other.
摘要翻译：利用本发明的ΔΣ调制器，可以容易地产生控制开关电路所需的多个时钟，并且可以在修改时钟频率的同时自动保持多个时钟的相位之间的相关性。环形振荡器由在Δ-Σ调制器中设置有差分放大器的三个延迟电路形成。时钟产生电路产生多个时钟，以通过延迟从环形振荡器输出的三相时钟来控制开关电路。环形振荡器的延迟电路中的差分放大器中的所有尾电流Ic和时钟产生电路的延迟电路中的差分放大器中的尾电流Ic成正比。

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