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11. 发明授权

US09696373B2 Verification and certification of an electronic component 有权
公开(公告)号：US09696373B2
公开(公告)日：2017-07-04
申请号：US14659843
申请日：2015-03-17
申请人： Airbus Defence and Space GmbH
发明人： Daniel J. Muench , Michael Paulitsch , Michael Honold , Wolfgang Schlecker
IPC分类号： G06F9/45 , H03K19/177 , G01R31/28 , G06Q10/00 , G01R31/00
CPC分类号： G01R31/28 , G01R31/00 , G06Q10/00 , H03K19/17764
摘要： A circuit is designed to be executed in a predeterminable operating mode of a plurality of operating modes. The circuit includes a first functional unit and a second functional unit. The first functional unit is designed as a static functional unit that in each of the plurality of operating modes of the circuit carries out a consistent function. The second functional unit is designed as an adaptable functional unit that is designed to be configured, prior to the circuit being put into service, according to a first configuration of a plurality of different configurations and during the operating time of the circuit to maintain the first configuration so that the first configuration of the second functional unit defines the predeterminable operating mode of the circuit. This makes it possible to reduce the verification expenditure for the circuit because verification can be limited to the adaptable functional unit.

12. 发明申请

US20170179958A1 LOGICAL ELEMENTS WITH SWITCHABLE CONNECTIONS FOR MULTIFUNCTION OPERATION 审中-公开
公开(公告)号：US20170179958A1
公开(公告)日：2017-06-22
申请号：US15443612
申请日：2017-02-27
申请人： Wave Computing, Inc.
发明人： Christopher John Nicol
IPC分类号： H03K19/0175 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/1776 , H03K19/17764
摘要： Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

13. 发明申请

US20160266964A1 PROGRAMMABLE LOGIC CIRCUIT DEVICE AND ERROR DETECTION METHOD THEREFOR 审中-公开
标题翻译：可编程逻辑电路设备及其错误检测方法
公开(公告)号：US20160266964A1
公开(公告)日：2016-09-15
申请号：US15059355
申请日：2016-03-03
申请人： FUJITSU LIMITED
发明人： Shinichiro Uekusa
IPC分类号： G06F11/10 , G11C7/00 , G11C29/44
CPC分类号： G06F11/1004 , G11C29/44 , G11C29/70 , G11C2029/0411 , H03K19/17764
摘要： A programmable logic circuit device has a configuration memory that stores configuration data; a programmable logic circuit in which a logic circuit is configured based on the configuration data stored in the configuration memory; a control circuit that sequentially and repeatedly reads, from the configuration memory, target configuration data corresponding to an error-check-target circuit in the programmable logic circuit, from among the configuration data in the configuration memory and; and an error detection circuit that executes an error check on the target configuration data read by the control circuit.
摘要翻译：可编程逻辑电路装置具有存储配置数据的配置存储器; 可编程逻辑电路，其中逻辑电路基于存储在配置存储器中的配置数据配置; 控制电路，从配置存储器中顺序地和重复地从配置存储器中的配置数据中读出与可编程逻辑电路中的错误检查目标电路相对应的目标配置数据; 以及错误检测电路，对由控制电路读取的目标配置数据执行错误检查。

14. 发明授权

US09437260B2 Reprogrammable logic device resistant to radiations 有权
标题翻译：可重复编程的逻辑器件耐辐射
公开(公告)号：US09437260B2
公开(公告)日：2016-09-06
申请号：US14395555
申请日：2013-04-24
申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
发明人： Guillaume Prenat , Olivier Goncalves
IPC分类号： G11C7/10 , H03K19/003 , H03K19/177
CPC分类号： G11C7/1045 , H03K19/0033 , H03K19/1776 , H03K19/17764 , H03K19/17776 , H03K19/1778
摘要： The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell comprising first and second resistance-switching elements, each being programmable so as to have one of a first and of a second resistance value representative of the refresh data; and a read-write circuit adapted for periodically refreshing the configuration data on the basis of the refresh data.
摘要翻译：本发明涉及一种包括多个基本补丁的可再编程逻辑器件，每个补丁包括：由一个或多个存储配置数据的易失性存储单元配置的至少一个逻辑块; 以及存储器，包括：存储刷新数据的多个非易失性存储单元，每个非易失性存储单元包括第一和第二电阻切换元件，每个非易失性存储单元可编程为具有第一和第二电阻值代表中的一个的刷新数据; 以及适于基于刷新数据周期性地刷新配置数据的读写电路。

15. 发明授权

US09385725B2 Runtime loading of configuration data in a configurable IC 有权
公开(公告)号：US09385725B2
公开(公告)日：2016-07-05
申请号：US14664755
申请日：2015-03-20
申请人： Altera Corporation
发明人： Brad Hutchings , Jason Redgrave , Teju Khubchandani , Herman Schmit , Steven Teig
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1731 , H03K19/177 , H03K19/17704 , H03K19/17736 , H03K19/17748 , H03K19/17756 , H03K19/17764
摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

16. 发明申请

US20160179904A1 LADDER PROGRAM RETRIEVAL DEVICE CAPABLE OF RETRIEVING LADDER CIRCUITS BASED ON SPECIFIED SIGNAL OPERATION CONDITIONS 审中-公开
标题翻译：基于指定信号操作条件检测梯形电路的梯形图程序检索装置
公开(公告)号：US20160179904A1
公开(公告)日：2016-06-23
申请号：US14973792
申请日：2015-12-18
申请人： FANUC Corporation
发明人： Mitsuru MOCHIZUKI
IPC分类号： G06F17/30 , H03K19/177
CPC分类号： H03K19/17764
摘要： Provided is a ladder program retrieval device that includes: search condition specification unit for specifying, as search conditions, a plurality of signals and a logical operation relationship between any two signals included in the plurality of signals; search signal presence determination unit for determining, for each of the plurality of ladder circuits included in the ladder program, whether the ladder circuit includes all of the plurality of signals specified in the search conditions; and search logic presence determination unit for determining, for each of the ladder circuits determined by the search signal presence determination unit to include all of the signals specified in the search conditions, whether or not the ladder circuit includes the logical operation relationship.
摘要翻译：提供了一种梯形图程序检索装置，其包括：搜索条件指定单元，用于指定多个信号中的多个信号和包括在所述多个信号中的任意两个信号之间的逻辑运算关系的搜索条件; 搜索信号存在确定单元，用于为梯形图程序中包括的多个梯形电路中的每一个确定梯形图电路是否包括在搜索条件中指定的所有多个信号; 以及搜索逻辑存在确定单元，用于针对由搜索信号存在确定单元确定的每个梯形电路确定包括在搜索条件中指定的所有信号，梯形图电路是否包括逻辑运算关系。

17. 发明授权

US09372221B1 Partial discharge signal normalization 有权
标题翻译：部分放电信号归一化
公开(公告)号：US09372221B1
公开(公告)日：2016-06-21
申请号：US14838884
申请日：2015-08-28
申请人： Adam Bierman
发明人： Adam Bierman
IPC分类号： H03K19/00 , H03K19/173 , G01R31/14 , H03K19/177 , G01R31/12
CPC分类号： G01R31/14 , G01R31/1245 , H03K19/17764
摘要： The disclosure herein relates to a field-programmable gate array for detecting and normalizing partial discharges in a digital signal. The field-programmable gate array includes a filter that receives the digital signal and isolates high frequency information from the digital signal. The field-programmable gate array then normalizes the high frequency information by a compensation value to produce a normalized signal. Further, a comparator of the field-programmable gate array can determine whether the normalized signal exceeds a threshold input. In turn, a counter of the field-programmable gate array increments a counter value in response to each determination that the high frequency information exceeds the threshold input.
摘要翻译：本文的公开内容涉及用于检测和归一化数字信号中的部分放电的现场可编程门阵列。现场可编程门阵列包括接收数字信号并从数字信号隔离高频信息的滤波器。现场可编程门阵列然后通过补偿值对高频信息进行标准化，以产生归一化信号。此外，现场可编程门阵列的比较器可以确定归一化信号是否超过阈值输入。反过来，响应于高频信息超过阈值输入的每个确定，现场可编程门阵列的计数器递增计数器值。

18. 发明申请

US20160094229A1 CHIP AND METHOD FOR IDENTIFYING A CHIP 有权
标题翻译：用于识别芯片的芯片和方法
公开(公告)号：US20160094229A1
公开(公告)日：2016-03-31
申请号：US14868451
申请日：2015-09-29
申请人： Infineon Technologies AG
发明人： Georg TEMPEL , Rolf-Peter VOLLERTSEN
IPC分类号： H03K19/177 , H03K19/003
CPC分类号： H03K19/17708 , G11C13/0007 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/20 , G11C16/26 , G11C2213/32 , H03K19/00315 , H03K19/17764
摘要： A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.
摘要翻译：芯片包括具有多个晶体管并被配置为执行逻辑数据处理功能的逻辑电路，在执行数据处理功能时晶体管沿第一方向工作;以及读出电路，被配置为控制逻辑电路以这样的方式使得晶体管在与第一方向相反的第二方向上操作，并且被配置为基于在第二方向上操作晶体管时来自逻辑电路的输出来确定逻辑电路的标识。

19. 发明授权

US09263463B2 Semiconductor integrated circuit, programmable logic device, method of manufacturing semiconductor integrated circuit 有权
标题翻译：半导体集成电路，可编程逻辑器件，半导体集成电路制造方法
公开(公告)号：US09263463B2
公开(公告)日：2016-02-16
申请号：US14500349
申请日：2014-09-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto
IPC分类号： H03K19/177 , G06F7/38 , H01L27/118 , G11C16/04 , H01L21/28 , H01L29/66 , H01L27/02 , H01L29/788 , H01L29/792 , H01L27/115 , G11C16/10 , H01L21/265
CPC分类号： H01L27/11803 , G11C16/04 , G11C16/0441 , G11C16/10 , H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L27/11573 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H03K19/17764 , H03K19/17792
摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
摘要翻译：根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

20. 发明授权

US09252778B2 Robust flexible logic unit 有权
标题翻译：强大的灵活逻辑单元
公开(公告)号：US09252778B2
公开(公告)日：2016-02-02
申请号：US14754162
申请日：2015-06-29
申请人： Scaleo Chip
发明人： Farid Tahiri , Pierre Dominique Xavier Garaccio
IPC分类号： H03K19/177
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/17756 , H03K19/17764
摘要： A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.
摘要翻译：强大的灵活逻辑单元（FLU）主要是将其作为嵌入式现场可编程门阵列（EFPGA）而非排他性使用。该单元由多个可编程构建块瓦片组成，其中多个可排列的列和瓦片阵列，以及通过瓦片和逐列的编程瓦片，使用使用锁定位的锁存器，锁存器是使用作为提供了位流。奇数和偶数时钟的方案可防止锁定透明度，并确保加载的数据被正确锁定，以防止覆盖。强大的FLU进一步配备了循环冗余检查功能，以提供故障列配置的指示。本发明还提供了将单个FLU分离成多个独立的可重新配置的FLU部分，具有独立的用户时钟和复位，用于实现多个独立的功能或用于为关键功能建立冗余。

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