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11. 发明申请

US20170179881A1 Common-Mode Impedance Network for Reducing Sensitivity in Oscillators 有权
公开(公告)号：US20170179881A1
公开(公告)日：2017-06-22
申请号：US14970865
申请日：2015-12-16
申请人： SILICON LABORATORIES INC.
发明人： Aaron J. Caffee
IPC分类号： H03B5/08
CPC分类号： H03B5/08 , H03B5/12 , H03B5/1212 , H03B5/1228 , H03L1/00 , H03L1/026 , H03L7/0812
摘要： A low-complexity differential inductor and common-mode impedance network for reducing effects of flicker noise in an oscillator output signal have been disclosed. An oscillator includes a planar conductive loop comprising a first terminal, a second terminal, and a center tap. The planar conductive loop is formed from a first conductive layer above an integrated circuit substrate. The center tap is coupled to a first power supply node. The oscillator includes a planar conductive structure extending from a first point proximate to the center tap. The planar conductive structure extends along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal. The planar conductive structure may be formed from the first conductive layer and may be directly coupled to the center tap.

12. 发明申请

US20160226443A1 INTEGRATED CLOCK GENERATOR AND METHOD THEREFOR 有权
标题翻译：集成时钟发生器及其方法
公开(公告)号：US20160226443A1
公开(公告)日：2016-08-04
申请号：US15096612
申请日：2016-04-12
申请人： Silicon Laboratories Inc.
发明人： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1234 , H03B5/12 , H03B5/1265 , H03B5/36 , H03L1/00 , H03L1/026 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/183 , H03L7/1976 , H03L7/22 , H03L7/23
摘要： An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
摘要翻译：集成时钟发生器包括可调谐LC振荡器，可调频率合成器和处理器。可调LC振荡器具有用于接收振荡器控制信号的输入端和用于提供振荡器时钟信号的输出端。可调频率合成器具有耦合到可调谐LC振荡器的输出的时钟输入，用于接收合成器控制信号的控制输入和用于提供时钟输出信号的输出。处理器具有用于接收数据输入信号的输入端，用于提供振荡器控制信号的第一输出端和用于提供合成器控制信号的第二输出端。处理器提供振荡器控制信号和合成器控制信号，使得可调谐频率合成器以由数据输入信号指示的频率生成输出时钟信号，并且响应于动态条件进一步提供合成器控制信号。

13. 发明申请

US20160173137A1 RECEIVER AND VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：接收器和电压控制振荡器
公开(公告)号：US20160173137A1
公开(公告)日：2016-06-16
申请号：US14971086
申请日：2015-12-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tuan Thanh TA , Akihide SAI , Masanori FURUTA
IPC分类号： H04B1/00 , H04L25/08 , H04B1/16 , H03B9/14 , H03F3/19
CPC分类号： H04B1/0007 , H03B5/12 , H03B9/141 , H03B2201/0208 , H03B2201/0258 , H03F3/19 , H03F2200/294 , H03L7/0991 , H03L7/22 , H03L2207/06 , H04B1/16
摘要： According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to--digital converter and an input sensitivity controller. In the voltage controlled oscillator, input sensitivity relative to a baseband signal is controlled based on an input sensitivity control signal. The voltage controlled oscillator oscillates at a frequency controlled by a voltage of the baseband signal to generate an oscillation signal. . The frequency--to-digital converter performs frequency-to-digital conversion of the oscillation signal to generate a digital signal. The input sensitivity controller generates the input sensitivity control signal based on the digital signal.
摘要翻译：根据实施例，接收机包括压控振荡器，频数转换器和输入灵敏度控制器。在压控振荡器中，基于输入灵敏度控制信号来控制相对于基带信号的输入灵敏度。压控振荡器以由基带信号的电压控制的频率振荡以产生振荡信号。。频数转换器执行振荡信号的频数转换以产生数字信号。输入灵敏度控制器根据数字信号产生输入灵敏度控制信号。

14. 发明授权

US09306587B2 Oscillator circuit and configuration method thereof 有权
标题翻译：振荡电路及其配置方法
公开(公告)号：US09306587B2
公开(公告)日：2016-04-05
申请号：US14716879
申请日：2015-05-20
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Zhigang Fu
IPC分类号： H03L7/24 , H03B5/24 , H03B5/12
CPC分类号： H03L7/24 , H03B5/12 , H03B5/24 , H03L7/00
摘要： The present disclosure provides an oscillator circuit. The oscillator circuit includes a signal selecting unit, a control voltage generating unit, a reference voltage generating unit, an output adjusting unit, and a frequency-dividing unit. The signal selecting unit is configured to select a reference signal or a frequency-divided signal as an input signal. The control voltage generating unit is configured to generate a control voltage based on the input signal. The reference voltage generating unit is configured to generate a reference voltage. The output adjusting unit is configured to generate an output signal based on the control voltage and the reference voltage. The frequency-dividing unit is configured to divide the frequency of the output signal and generate the frequency-divided signal.
摘要翻译：本公开提供了一种振荡器电路。振荡电路包括信号选择单元，控制电压产生单元，参考电压产生单元，输出调整单元和分频单元。信号选择单元被配置为选择参考信号或分频信号作为输入信号。控制电压产生单元被配置为基于输入信号产生控制电压。参考电压产生单元被配置为产生参考电压。输出调整单元被配置为基于控制电压和参考电压产生输出信号。分频单元被配置为分频输出信号的频率并产生分频信号。

15. 发明申请

US20150048892A1 LOW-NOISE CURRENT SOURCE 有权
标题翻译：低噪声电流源
公开(公告)号：US20150048892A1
公开(公告)日：2015-02-19
申请号：US13966001
申请日：2013-08-13
申请人： Analog Devices, Inc.
发明人： William T. Boles , Michael R. Elliott
IPC分类号： H02M3/156 , H03F3/16
CPC分类号： H02M3/156 , G05F3/262 , H03B5/12 , H03F3/16 , H03F3/68
摘要： In one example embodiment, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.
摘要翻译：在一个示例性实施例中，提供电流源以限制噪声和偏移。在一个实施例中，提供源晶体管，源极在漏极处。反馈网络从源节点运行到门。反馈网络通过跨导产生电压增益，例如晶体管。还提供适当的电容器，并且设置两对开关以通过在开关电容器架构中的增益和钳位模式之间切换来提供偏移消除。

16. 发明授权

US08847652B2 Reconfigurable and auto-reconfigurable resonant clock 有权
标题翻译：可重构和自动重构谐振时钟
公开(公告)号：US08847652B2
公开(公告)日：2014-09-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： G06F1/10 , H03K5/15
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

17. 发明授权

US11909355B2 Multi-core oscillator with transient supply voltage assisted mode switching 有权
公开(公告)号：US11909355B2
公开(公告)日：2024-02-20
申请号：US17942850
申请日：2022-09-12
申请人： Apple Inc.
发明人： Hongrui Wang , Abbas Komijani
IPC分类号： H03L1/00 , H04B1/40 , H03B5/12
CPC分类号： H03B5/12 , H03L1/00 , H04B1/40 , H03B2200/009 , H03B2200/0092 , H03B2201/038
摘要： To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).

18. 发明申请

US20190207640A1 WIRELESS SYSTEM HAVING LOCAL OSCILLATOR SIGNAL DERIVED FROM REFERENCE CLOCK OUTPUT OF ACTIVE OSCILLATOR THAT HAS NO ELECTROMECHANICAL RESONATOR 审中-公开
公开(公告)号：US20190207640A1
公开(公告)日：2019-07-04
申请号：US16152391
申请日：2018-10-04
申请人： MEDIATEK INC.
发明人： Jui-Lin Hsu , Chao-Ching Hung , Tzu-Chin Lin , Wei-Hsiu Hsu , Yu-Li Hsueh , Jing-Hong Conan Zhan , Chih-Ming Hung
IPC分类号： H04B1/403 , H03B5/12 , G01S7/03
CPC分类号： H04B1/403 , G01S7/03 , G01S7/032 , H03B5/12 , H03B2200/008 , H03K5/135 , H04B7/2662
摘要： A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

19. 发明申请

US20180248555A1 RING OSCILLATOR STRUCTURES TO DETERMINE LOCAL VOLTAGE VALUE 审中-公开
公开(公告)号：US20180248555A1
公开(公告)日：2018-08-30
申请号：US15445587
申请日：2017-02-28
申请人： International Business Machines Corporation
发明人： Keith A. Jenkins , Peilin Song , James H. Stathis , Franco Stellari
IPC分类号： H03L1/00 , H03K3/03
CPC分类号： H03L1/00 , G01R31/2824 , G01R31/2851 , H03B1/00 , H03B5/12 , H03B5/1215 , H03B5/30 , H03B5/36 , H03K3/0315 , H04L9/3278
摘要： An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

20. 发明授权

US09876469B1 Voltage-controlled oscillator with mask-selectable performance 有权
公开(公告)号：US09876469B1
公开(公告)日：2018-01-23
申请号：US15163956
申请日：2016-05-25
申请人： MACOM Technology Solutions Holdings, Inc.
发明人： Wayne M. Struble , Eoin Carey , Ronan G. Brady , Shane M. Collins
IPC分类号： H03K3/282 , H03B5/12
CPC分类号： H03B5/1243 , H01L23/5222 , H01L23/5227 , H01L25/0655 , H01L25/50 , H01L2924/0002 , H03B5/12 , H03B5/1218 , H03B5/1231 , H03B5/24 , H03L7/099 , H01L2924/00
摘要： An apparatus includes a substrate, a capacitance die and an exciter die. The capacitance die is generally mounted on the substrate and may be configured to vary a frequency of a signal in an inductor. The exciter die is generally mounted on the substrate and may be configured to excite the signal. A particular one of the capacitance die and the exciter die may be fabricated with a die mask that has a plurality of available designs. The available designs generally customize the particular die to a plurality of configurations respectively. The capacitance die, the exciter die and the inductor may form a voltage-controlled oscillator.

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