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11. 发明申请

US20120305893A1 TRANSISTOR DEVICE 审中-公开
标题翻译：晶体管器件
公开(公告)号：US20120305893A1
公开(公告)日：2012-12-06
申请号：US13579825
申请日：2011-02-21
申请人： Jean-Pierre Colinge
发明人： Jean-Pierre Colinge
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/42392 , H01L29/66795 , H01L29/7851 , H01L29/78696 , H01L2029/7857
摘要： The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×1019 atom/cm3 results in that the device can operate as a junctionless transistor device.
摘要翻译：本发明提供了包括源极，漏极和连接沟道的晶体管器件，该沟道是适于允许源极和漏极之间的电流流动的纳米结构器件。该通道包括超高掺杂浓度并且具有与源极和/或漏极中相同的极性。基本上本发明的晶体管器件用作无连接，高掺杂的门控电阻器。在等于或超过1×1019原子/ cm3的晶体管高掺杂装置的最佳性能的上下文中，导致器件可以作为无连接晶体管器件工作。

12. 发明申请

US20120292681A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120292681A1
公开(公告)日：2012-11-22
申请号：US13473153
申请日：2012-05-16
申请人： Yoshinori IKEBUCHI , Yoshihiro TAKAISHI
发明人： Yoshinori IKEBUCHI , Yoshihiro TAKAISHI
IPC分类号： H01L29/78 , H01L29/94
CPC分类号： H01L29/8605 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/785 , H01L29/93 , H01L29/94 , H01L2029/7857
摘要： A semiconductor device includes a substrate having a groove in a periphery, a gate electrode partially embedded in the groove to sandwich the substrate from opposite directions by side walls of the groove, and a diffusion layer formed over the substrate and surrounded by the gate electrode. A resistance value of the diffusion layer is changed by changing a potential between the gate electrode and the diffusion layer.
摘要翻译：一种半导体器件包括：具有周边凹槽的基板，部分嵌入凹槽中的栅电极，用于通过沟槽的侧壁从相反方向夹持基板;以及扩散层，形成在该基板上并由栅电极包围。通过改变栅电极和扩散层之间的电位来改变扩散层的电阻值。

13. 发明申请

US20100320508A1 HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：水平金属半导体场效应晶体管
公开(公告)号：US20100320508A1
公开(公告)日：2010-12-23
申请号：US12677066
申请日：2008-09-12
申请人： Joseph E. Ervin , Trevor John Thornton
发明人： Joseph E. Ervin , Trevor John Thornton
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/8124 , H01L29/1037 , H01L29/42316 , H01L29/4238 , H01L29/47 , H01L29/66848 , H01L29/7832 , H01L29/7855 , H01L29/8126 , H01L2029/7857
摘要： The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESPET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.
摘要翻译：本发明提供了一种水平耗尽的金属半导体场效应晶体管（MESPET）。漏极区域，源区域和沟道区域形成在器件层中，使得漏极区域和源极区域彼此间隔开，并且沟道区域在漏极区域和源极区域之间延伸。第一和第二栅极触点形成在沟道区两侧的器件层中，因此第一和第二栅极触点也将位于源区和漏区的相对部分之间。利用该配置，施加到第一和第二栅极触点的电压有效地控制在沟道区的任一侧上形成的垂直耗尽区。

14. 发明申请

US20080303095A1 VARYING MUGFET WIDTH TO ADJUST DEVICE CHARACTERISTICS 审中-公开
标题翻译：改变MUGFET宽度以调整设备特性
公开(公告)号：US20080303095A1
公开(公告)日：2008-12-11
申请号：US11759710
申请日：2007-06-07
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L2029/7857
摘要： One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种集成电路，其包括具有第一鳍宽度和第一阈值电压的第一多栅极晶体管。集成电路还包括具有大于第一宽度的第二鳍宽度和小于第一阈值电压的第二阈值电压的第二多栅极晶体管。还公开了其它电路和方法。

15. 发明授权

US07173310B2 Lateral lubistor structure and method 有权
标题翻译：横向电阻结构和方法
公开(公告)号：US07173310B2
公开(公告)日：2007-02-06
申请号：US10908961
申请日：2005-06-02
申请人： Steven H. Voldman , Jack A. Mandelman
发明人： Steven H. Voldman , Jack A. Mandelman
IPC分类号： H01L27/01 , H01L27/12 , H01L29/00 , H01L31/0392
CPC分类号： H01L29/7391 , H01L27/0248 , H01L27/1203 , H01L29/785 , H01L2029/7857
摘要： An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device or may be connected to a reference voltage. The device may be used in digital or analog circuits.
摘要翻译：基于FINFET技术的ESD LUBISTOR结构在具有和不具有栅极的情况下采用垂直翅片（包含装置的源极，漏极和主体的薄垂直构件）。栅极可以连接到受保护的外部电极以形成自激活装置或者可以连接到参考电压。该器件可用于数字或模拟电路。

16. 发明授权

US10062706B2 Semiconductor device 有权
公开(公告)号：US10062706B2
公开(公告)日：2018-08-28
申请号：US15682492
申请日：2017-08-21
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yosuke Takeuchi , Eiji Tsukuda , Kenichiro Sonoda , Shibun Tsuda
IPC分类号： H01L29/792 , H01L27/11573 , H01L29/423 , H01L27/11565 , H01L29/78
CPC分类号： H01L27/11573 , H01L27/11565 , H01L29/42344 , H01L29/7851 , H01L29/7856 , H01L29/792 , H01L2029/7857
摘要： A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

17. 发明申请

US20180069052A1 SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开
公开(公告)号：US20180069052A1
公开(公告)日：2018-03-08
申请号：US15803732
申请日：2017-11-03
申请人： Monolithic 3D Inc.
发明人： Deepak C. Sekar , Zvi Or-Bach
IPC分类号： H01L27/24 , H01L27/22
CPC分类号： H01L27/2481 , H01L21/268 , H01L21/6835 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/105 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/10897 , H01L27/11 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/1203 , H01L27/1211 , H01L27/228 , H01L27/2436 , H01L27/249 , H01L29/42392 , H01L29/7841 , H01L29/785 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2029/7857 , H01L2221/6835
摘要： A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.

18. 发明申请

US20170345923A1 FINFET WITH P/N STACKED FINS AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20170345923A1
公开(公告)日：2017-11-30
申请号：US15367054
申请日：2016-12-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hung-Pin CHEN , Chi-Cherng JENG , Ru-Shang HSIAO , Li-Yi CHEN
IPC分类号： H01L29/78 , H01L29/423 , H01L29/36 , H01L21/265 , H01L29/16 , H01L21/306 , H01L29/66 , H01L29/417
CPC分类号： H01L29/785 , H01L21/26506 , H01L21/30604 , H01L21/845 , H01L27/1211 , H01L29/16 , H01L29/36 , H01L29/41791 , H01L29/42356 , H01L29/66795 , H01L29/775 , H01L2029/7857
摘要： A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type. The second semiconductor layer is stacked on and contacts the first semiconductor layer.

19. 发明授权

US09825133B2 Semiconductor device and related manufacturing method 有权
公开(公告)号：US09825133B2
公开(公告)日：2017-11-21
申请号：US15067741
申请日：2016-03-11
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Deyuan Xiao
IPC分类号： H01L23/535 , H01L29/10 , H01L29/06 , H01L29/24 , H01L29/775 , H01L29/78
CPC分类号： H01L29/1054 , H01L29/0649 , H01L29/24 , H01L29/775 , H01L29/785 , H01L2029/7857
摘要： A semiconductor device may include a gate electrode, an insulating layer, a first channel member, and a second channel member. The insulating layer may overlap the gate electrode. The first channel member may be positioned between the gate electrode and the insulating layer. The second channel member may be positioned between the gate electrode and the first channel member. A semiconductor material of the second channel member may be different from a semiconductor material of the first channel member.

20. 发明申请

US20160163844A1 Method and Structure for III-V FinFET 有权
标题翻译： III-V FinFET的方法和结构
公开(公告)号：US20160163844A1
公开(公告)日：2016-06-09
申请号：US15045325
申请日：2016-02-17
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L29/775 , H01L29/205 , H01L29/66 , H01L29/15
CPC分类号： H01L29/775 , H01L29/1033 , H01L29/155 , H01L29/205 , H01L29/401 , H01L29/66522 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L2029/7857
摘要： A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the Ill-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.
摘要翻译：一种用于制造半导体器件的方法包括在绝缘体上硅衬底上形成III-V族化合物半导体材料层中的散热片; 在所述翅片上形成半导体延伸部，所述半导体延伸部包括与所述III-V族化合物半导体层中形成所述散热片的材料不同的III-V族化合物半导体材料; 在翅片上横跨并垂直于翅片形成虚拟栅极结构和间隔物; 在与所述虚拟栅极结构相邻的所述衬底的顶表面上形成源极/漏极层; 平坦化源极/漏极层; 去除所述伪栅极结构以使所述鳍上的所述半导体延伸部的一部分露出; 去除所述半导体延伸部的暴露部分; 蚀刻半导体延伸部以切割间隔物; 以及形成替代栅极结构来代替去除的虚拟栅极结构并去除半导体延伸部的暴露部分。

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