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11. 发明授权

US09787196B2 Frequency jittering control circuit and the method thereof 有权
公开(公告)号：US09787196B2
公开(公告)日：2017-10-10
申请号：US15275165
申请日：2016-09-23
申请人： Monolithic Power Systems, Inc.
发明人： Siran Wang
IPC分类号： H02M3/335 , H03K7/08 , G11C27/02 , H02M1/08 , H02M1/44 , H02M1/00
CPC分类号： H02M3/33507 , G11C27/024 , H02M1/08 , H02M1/44 , H02M3/335 , H02M2001/0009 , H02M2001/0025 , H03K7/08
摘要： A control method of frequency jittering with a switching mode power supply, comprising: turning on and off a power switch of the switching mode power supply alternatively; updating a peak current signal of the switching mode power supply at a beginning of an on time of the power switch according to a length of a switching period before the beginning of the on time of the power switch, wherein the peak current signal varies as the length of the switching period changes.

12. 发明授权

US09741449B1 Sample and hold circuit 有权
公开(公告)号：US09741449B1
公开(公告)日：2017-08-22
申请号：US15231946
申请日：2016-08-09
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Pedro Barbosa Zanetta , Marcos Mauricio Pelicia
IPC分类号： H03K5/00 , H03K17/00 , G11C27/02 , H02M3/07 , H03K17/687
CPC分类号： H03K17/6872 , G11C27/024
摘要： Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.

13. 发明授权

US09685971B2 Successive comparison A/D conversion circuit 有权
公开(公告)号：US09685971B2
公开(公告)日：2017-06-20
申请号：US15299660
申请日：2016-10-21
申请人： OLYMPUS CORPORATION
发明人： Yasunari Harada
IPC分类号： H03M1/38 , G11C27/02 , H03M1/12
CPC分类号： H03M1/38 , G11C27/02 , G11C27/024 , H03M1/0682 , H03M1/1245 , H03M1/46
摘要： A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.

14. 发明申请

US20170125124A1 CHARGE INJECTION NOISE REDUCTION IN SAMPLE-AND-HOLD CIRCUIT 有权
公开(公告)号：US20170125124A1
公开(公告)日：2017-05-04
申请号：US14928524
申请日：2015-10-30
申请人： Sony Semiconductor Solutions Corporation
发明人： Noam Eshel , Golan Zeituni , Zvika Lupu
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C27/024
摘要： A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.

15. 发明申请

US20170098475A1 SAMPLING DEVICE 审中-公开
公开(公告)号：US20170098475A1
公开(公告)日：2017-04-06
申请号：US15173348
申请日：2016-06-03
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Ols HIDRI
IPC分类号： G11C27/02 , H03K5/24
CPC分类号： G11C27/02 , G11C27/024 , H03K5/2418 , H03K5/2427 , H03K5/2481 , H03K5/249 , H03M1/124
摘要： A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

16. 发明申请

US20170085821A1 DUAL SAMPLE-AND-HOLD CIRCUIT WITH RESISTIVE GAIN 审中-公开
公开(公告)号：US20170085821A1
公开(公告)日：2017-03-23
申请号：US15356500
申请日：2016-11-18
申请人： Sony Semiconductor Solutions Corporation
发明人： Noam Eshel , Golan Zeituni
IPC分类号： H04N5/378 , G11C27/02
CPC分类号： H04N5/378 , G11C27/024 , H02M11/00 , H03M3/30 , H04N5/374
摘要： An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.

17. 发明申请

US20170076823A1 TRACK AND HOLD WITH ACTIVE CHARGE CANCELLATION 审中-公开
标题翻译：跟踪和保持有效充电取消
公开(公告)号：US20170076823A1
公开(公告)日：2017-03-16
申请号：US15261303
申请日：2016-09-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Himanshu AGGRAWAL , Manar Ibrahim EL-CHAMMAS
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.
摘要翻译：轨道保持电路包括初级采样电容器，初级开关晶体管和消除晶体管。主开关晶体管被配置为提供将输入信号连接到初级采样电容器的轨道状态和将初级采样电容器的输入信号隔离的保持状态。消除晶体管耦合到初级采样电容器。取消晶体管被配置为在初级开关晶体管处于保持状态时，通过初级开关晶体管将主要采样电容器上的电荷注入到主要采样电容器上，从而抵消初级采样电容器的注入。

18. 发明申请

US20170062048A1 REGULATING MEMRISTOR SWITCHING PULSES 有权
标题翻译：调节脉冲开关脉冲
公开(公告)号：US20170062048A1
公开(公告)日：2017-03-02
申请号：US15307486
申请日：2014-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Ning Ge , Jianhua Yang , Adam L. Ghozeil , Brent Buchanan
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C27/024 , G11C2013/0054 , G11C2013/0066 , G11C2013/0076 , G11C2013/0092
摘要： A device for regulating memristor switching pulses is described. The device includes a voltage source to supply a voltage to a memristor. The device also includes a voltage detector to detect a memristor voltage. The memristor voltage is based on an initial resistance state of the memristor and the voltage supplied by the voltage source. The device also includes a comparator to compare the memristor voltage with a target voltage value for the memristor. The device also includes a feedback loop to indicate to a control switch when the memristor voltage is at least equal to the target voltage value. The device also includes a control switch to cut off the memristor from the voltage source when the memristor voltage is at least equal to the target voltage value.
摘要翻译：描述了用于调节忆阻器切换脉冲的装置。该装置包括用于向忆阻器提供电压的电压源。该装置还包括检测忆阻器电压的电压检测器。忆阻器电压基于忆阻器的初始电阻状态和由电压源提供的电压。该器件还包括比较器，用于将忆阻器电压与忆阻器的目标电压值进行比较。当存储器电压至少等于目标电压值时，该装置还包括反馈回路以向控制开关指示。该装置还包括控制开关，当忆阻器电压至少等于目标电压值时，该开关用于从忆阻器与电压源切断。

19. 发明申请

US20170041016A1 SUCCESSIVE COMPARISON A/D CONVERSION CIRCUIT 有权
标题翻译：成功的比较A / D转换电路
公开(公告)号：US20170041016A1
公开(公告)日：2017-02-09
申请号：US15299660
申请日：2016-10-21
申请人： OLYMPUS CORPORATION
发明人： Yasunari Harada
IPC分类号： H03M1/38 , H03M1/12 , G11C27/02
CPC分类号： H03M1/38 , G11C27/02 , G11C27/024 , H03M1/0682 , H03M1/1245 , H03M1/46
摘要： A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.
摘要翻译：连续比较A / D转换电路包括：包括差分放大电路的比较电路，差分放大电路包括一对差分输入端，放大输入到该对差分输入端的一对第一差分信号，并输出一对第二差分信号，以及比较从差分放大电路输出的第二差分信号的电压的锁存电路，保持比较结果，并输出保留的比较结果; 基于比较结果生成对应于第一差分信号的数字信号的数字电路; 产生基于数字信号的参考信号的算术电路，通过从第三差分信号中减去参考信号或将参考信号与第三差分信号相加来产生第一差分信号，并将产生的第一差分信号输出到对的差分输入端子; 和控制电路。

20. 发明授权

US09460808B2 Method and device for controlling a sample and hold circuit 有权
标题翻译：用于控制采样和保持电路的方法和装置
公开(公告)号：US09460808B2
公开(公告)日：2016-10-04
申请号：US14549291
申请日：2014-11-20
申请人： STMicroelectronics (Rousset) SAS
发明人： Bruno Gailhard , Yohan Joly
IPC分类号： H03K5/00 , G11C27/02 , G11C29/50 , G11C29/02 , H03K3/0231
CPC分类号： G11C27/024 , G11C29/023 , G11C29/028 , G11C29/50016 , H03K3/0231
摘要： A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.
摘要翻译：提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。至少一个主电流被传送到至少一个辅助电容器。从至少一个辅助电容器的充电和放电产生初始脉冲信号。采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

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