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11. 发明申请

US20050220240A1 Clock synchroniser and clock and data recovery apparatus and method 审中-公开
标题翻译：时钟同步器和时钟与数据恢复装置及方法
公开(公告)号：US20050220240A1
公开(公告)日：2005-10-06
申请号：US10900347
申请日：2004-07-28
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： G06F5/06 , G06F5/12 , H03L7/10 , H03L7/197 , H04J3/06 , H04L7/00 , H04L7/033 , H04L25/05
CPC分类号： H03L7/197 , G06F5/06 , G06F5/12 , G06F2205/061 , H03L7/10 , H04J3/0632
摘要： A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.
摘要翻译：时钟同步器以及并入时钟同步器的时钟和数据恢复装置与对应的时钟同步方法一起被描述。时钟同步器包含弹性缓冲器。接收到的时钟信号用于将数据进入缓冲器，本地生成的时钟用于将数据从缓冲器中提取出来。使用PLL合成本地时钟，并且使用来自弹性缓冲器的填充级信号来控制本地时钟频率，以保持缓冲器中期望的平均数据量，从而实现接收和本地时钟的同步。在优选实施例中，填充电平信号用于控制PLL的反馈路径中的可变分频器，其被提供有高度稳定的参考信号。因此产生了同步和低抖动的本地时钟。优选地，弹性缓冲器使用具有相对宽的字宽的计数器，并且由字的几个最低有效位提供了大大减少的深度，读和写指针的存储阵列。

12. 发明授权

US06711227B1 Synchronizing method and apparatus 有权
公开(公告)号：US06711227B1
公开(公告)日：2004-03-23
申请号：US09498162
申请日：2000-02-04
申请人： Tarek Kaylani , Fang Lu , Henry Samueli
发明人： Tarek Kaylani , Fang Lu , Henry Samueli
IPC分类号： H04L2540
CPC分类号： G06F5/14 , G06F1/025 , G06F5/12 , G06F2205/061 , G06F2205/126 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/0996 , H03L7/23 , H04J3/062
摘要： To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal. A phase locked loop that synchronizes the phase shifted signal generating oscillator to a frequency reference is nested in the control loop that selects one of the phase shifted signals as the output signal.

13. 发明申请

US20040013093A1 Method and device for the clocked output of asynchronously received digital signals 有权
公开(公告)号：US20040013093A1
公开(公告)日：2004-01-22
申请号：US10618378
申请日：2003-07-11
申请人： Infineon Technologies AG
发明人： Stefan Eder , Gunther Fenzl
IPC分类号： H04L005/26
CPC分类号： G06F5/14 , G06F2205/061 , H04J3/0632
摘要： With regard to the asynchronous transmission of digital values between a transmitter, from which the digital values are transmitted at a first frequency and a receiver (A, B), in which the received digital values are further processed and in particular outputted at a second frequency, it is never possible to harmonize the first frequency with the second frequency. In consequence as a result of frequency differences never to be harmonized an overflow or under-run of the transmitted digital values occurs. In order to prevent this and to synchronize the frequency on the side of the receiver (A, B) for processing received digital values to the frequency on the side of the transmitter (A, B) at which the digital values are transmitted, the amount of the digital values received in relation to the time by the receiver (A, B) is determined and dependent on this, an output clock is set so that the digital values are outputted or further processed at the frequency, with which on average they have been received by the receiver (A, B). The method is particularly suitable, if data is transmitted bi-directionally between two subscribers (A, B) and digital values received at the same frequency by both subscribers (A, B) are outputted in analog form and analog input signals are digitized and each transmitted to the other subscriber (A, B). In this case the separate clock for outputting received digital values can be synchronized on the basis of the amount of digital values by either of the two subscribers (A, B) or even by both subscribers (A, B). Advantageously the two subscribers (A, B) are IP telephones for providing a telephone service via a communication network. The amount of incoming digital values can be evaluated by a synchronizing logic (SL), which is arranged within a clock generation unit (CGU) together with an oscillator (OSC), controlled by the synchronizing logic (SL) in such a way that an operating clock (fA) produced by it for a subscriber (A) ensures further processing of the received digital values at the same frequency, with which the digital values are received over the average time.

14. 发明申请

US20020034273A1 System and method for clock synchronization for USB sink device 失效
标题翻译： USB接收器设备的时钟同步系统和方法
公开(公告)号：US20020034273A1
公开(公告)日：2002-03-21
申请号：US09908979
申请日：2001-07-20
发明人： Steven Donald Spence , Nikolai Nikolov , Rudolf Ladyzhenski
IPC分类号： H04L007/00 , H04L025/00 , H04L025/40 , H04L023/00
CPC分类号： G06F5/06 , G06F2205/061 , H04J3/0632
摘要： In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.
摘要翻译：在数据宿设备与由USB耦合的数据源设备进行自适应同步的方法中，以代表源设备的数据速率的平均数据速率接收数据并将其存储在宿设备的缓冲器中。基于输入数据包大小和输出数据包大小确定缓冲区的数据级别。将缓冲器的累积数据级别与阈值级别进行比较。当累加数据电平超过阈值电平时，对信宿设备的时钟频率进行校正。

15. 发明授权

US5875354A System for synchronization by modifying the rate of conversion by difference of rate between first clock and audio clock during a second time period 失效
标题翻译：用于通过在第二时间段期间通过第一时钟和音频时钟之间的速率差来修改转换速率的同步系统
公开(公告)号：US5875354A
公开(公告)日：1999-02-23
申请号：US609395
申请日：1996-03-01
申请人： Paul Charlton , Keith Gurganus
发明人： Paul Charlton , Keith Gurganus
IPC分类号： G06F5/06 , G06F9/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： A method and apparatus for synchronizing the presentation of time dependent data to a first dock having a first frequency is disclosed. First, a rate conversion is performed on a data stream for a first time period. Second, the rate of conversion is modified to provide a modified rate of conversion. Third, a rate of conversion having a modified rate of conversion is performed on the data stream for a second time period. The second and third steps are repeated until all samples in the data stream are presented. The rate of conversion is modified from one period to the next based on a measurement of the difference between a rate for the first clock and the rate of a second less precise clock.
摘要翻译：公开了一种用于将时间相关数据的呈现同步到具有第一频率的第一坞站的方法和装置。首先，对第一时间段的数据流执行速率转换。第二，修改转换率以提供修改的转换率。第三，对数据流进行第二时间段的具有修改的转换率的转换率。重复第二和第三步骤，直到呈现数据流中的所有样本。基于第一时钟的速率和第二个较不精确的时钟的速率之间的差的测量，将转换率从一个周期修改为下一个周期。

16. 发明授权

US5862410A System for controlling a variable source by the feedback of the running mode, and relevant circuit 失效
标题翻译：通过运行模式的反馈控制可变源的系统，以及相关电路
公开(公告)号：US5862410A
公开(公告)日：1999-01-19
申请号：US989728
申请日：1992-12-11
申请人： Luigi Ronchetti , Mario Stroppiana
发明人： Luigi Ronchetti , Mario Stroppiana
IPC分类号： G06F5/10 , G06F5/14 , H04N7/12 , H04N7/26
CPC分类号： G06F5/14 , G06F2205/061
摘要： A system for controlling the rate of flow of data generated by a variable rate data source and fed to a buffer which outputs the data at a constant bit rate. The operating mode, which sets the bit rate of the variable rate data source, is determined not only by the degree to which the buffer is filled, but also by the immediately preceding operating mode. The feedback of the operating mode results in an hysteresis effect on the mode, thus reducing the number of changes of the rate of data generation and thereby increasing the transmission quality of the data generated and output from the system.
摘要翻译：一种用于控制由可变速率数据源产生的数据流的速率并被馈送到以恒定比特率输出数据的缓冲器的系统。设定可变速率数据源的比特率的操作模式不仅由缓冲器填充的程度决定，而且由紧接着的前一操作模式确定。操作模式的反馈导致对模式的滞后效应，从而减少了数据生成速率的变化数量，从而增加了从系统产生和输出的数据的传输质量。

17. 发明授权

US5513326A System for optimizing data transfer 失效
标题翻译：优化数据传输系统
公开(公告)号：US5513326A
公开(公告)日：1996-04-30
申请号：US434797
申请日：1995-05-04
申请人： Robert A. Nute
发明人： Robert A. Nute
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F2205/061
摘要： Optimizing data transfer to a storage device by providing a speed control circuit which adjusts, in a continuously varying manner, a transfer rate of a storage device according to utilization of a data buffer.
摘要翻译：通过提供速度控制电路来优化数据传输到存储设备，该速度控制电路以连续变化的方式根据数据缓冲器的利用率调整存储设备的传送速率。

18. 发明授权

US5502752A Clock rate matching in independent networks 失效
标题翻译：独立网络中的时钟速率匹配
公开(公告)号：US5502752A
公开(公告)日：1996-03-26
申请号：US49248
申请日：1993-04-20
申请人： Nimrod Averbuch , Steven V. Schatz
发明人： Nimrod Averbuch , Steven V. Schatz
IPC分类号： H04L7/00 , G06F5/06 , H04J3/06 , H04J3/07 , H04J3/16 , H04L7/02 , H04L7/08 , H04L25/05 , H04Q7/22 , H04Q7/24 , H04Q7/26 , H04Q7/30 , H04J3/22
CPC分类号： H04L25/05 , G06F5/06 , H04J3/07 , H04J3/1635 , H04L7/02 , G06F2205/061
摘要： An apparatus and method for clock rate matching in independent networks is disclosed. The apparatus accepts data from a modem (126) into a buffer (400) and determines the difference between the rate of the data entering the buffer (400) at the modem clock rate to the rate of data exiting the buffer (400) at the clock rate used by the apparatus. Depending on the rate difference, the apparatus either speeds up or slows down the data rate accordingly.
摘要翻译：公开了一种用于独立网络中的时钟速率匹配的装置和方法。该设备接受来自调制解调器（126）的数据进入缓冲器（400），并且以调制解调器时钟速率确定进入缓冲器（400）的数据的速率与在该缓冲器（400）处的数据的速率之间的差异该设备使用的时钟频率。根据速率差异，设备可以相应地加快或减慢数据速率。

19. 发明授权

US5027351A Asynchronous time division communication system 失效
标题翻译：异步时分通信系统
公开(公告)号：US5027351A
公开(公告)日：1991-06-25
申请号：US415274
申请日：1989-09-18
申请人： Martin L. F. De Prycker , Mark L. M. R. Ryckebusch , Peter I. A. Barri
发明人： Martin L. F. De Prycker , Mark L. M. R. Ryckebusch , Peter I. A. Barri
IPC分类号： G06F5/06 , H04J3/06 , H04L7/10 , H04L12/54
CPC分类号： H04J3/0632 , G06F5/06 , H04L12/56 , G06F2205/061 , H04L7/10
摘要： An asynchronous time division communication system having at least one station including a buffer and an associated processor for writing data packets into said buffer at a sending clock frequency, and for reading data packets from said buffer at a receiving clock frequency. The processor is further capable of assessing the real packet filling level of the buffer and adjusting the receiving clock frequency in corresponding relationship to the assessed real packet filling level. The processor calculates a mean packet filling level after a measured time has elapsed by using the mean of m successively assessed real packet filling levels of said buffer and using the calculated mean packet filling level for adjusting the receiving clock frequency.
摘要翻译：一种异步时分通信系统，具有包括缓冲器和相关处理器的至少一个站，用于以发送时钟频率将数据分组写入所述缓冲器，并以接收时钟频率从所述缓冲器读取数据分组。处理器还能够评估缓冲器的实际分组填充级别并且以与所评估的真实分组填充级别对应的关系调整接收时钟频率。处理器通过使用连续评估的所述缓冲器的实际分组填充级别的平均值并使用计算的平均分组填充级别来调整接收时钟频率，在经过测量时间之后计算平均分组填充水平。

20. 发明授权

US4718074A Dejitterizer method and apparatus 失效
标题翻译：除虫剂方法和装置
公开(公告)号：US4718074A
公开(公告)日：1988-01-05
申请号：US843668
申请日：1986-03-25
申请人： Earl L. Mannas , Thomas H. Johnson, Jr.
发明人： Earl L. Mannas , Thomas H. Johnson, Jr.
IPC分类号： G06F5/06 , H04J3/06 , H04L7/00
CPC分类号： H04J3/0626 , G06F5/06 , G06F2205/061
摘要： Dejitterizer apparatus is disclosed which uses a counter to track the number of bits stored in a 64-bit FIFO buffer. The counter is incremented on a falling edge of pulses of a timing pulse signal, nominally 6.176 Mhz, that coincides with a pulse of a jittered, nominally 1.554 Mhz, clock pulse signal derived from a jittered T1 signal applied to the input of the apparatus. The counter is decremented on the rising edge of pulses of a local clock pulse signal which is derived from the timing pulse signal. The bits are stored in the buffer in response to pulses of the jittered clock pulse signal. Output from the buffer in response to timing pulses derived from the local clock pulse signal is enabled when the counter indicates that the buffer is one-half full. The frequency of the local clock pulse signal is a function of the average frequency of the jittered clock pulse signal over more than sixteen jittered clock periods.
摘要翻译：公开了一种使用计数器来跟踪存储在64位FIFO缓冲器中的比特数的脱粒器装置。计数器在定时脉冲信号的脉冲的下降沿递增，标称为6.176Mhz，其与从施加到设备的输入端的抖动的T1信号得到的抖动的标称的1.554Mhz的脉冲信号相一致。计数器在定时脉冲信号导出的本地时钟脉冲信号的脉冲的上升沿递减。响应于抖动的时钟脉冲信号的脉冲，这些位被存储在缓冲器中。当计数器指示缓冲器为一半满时，使能响应于从本地时钟脉冲信号导出的定时脉冲从缓冲器输出。本地时钟脉冲信号的频率是超过十六个抖动时钟周期的抖动时钟脉冲信号的平均频率的函数。

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