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11. 发明授权

US09940235B2 Method and system for valid memory module configuration and verification 有权
公开(公告)号：US09940235B2
公开(公告)日：2018-04-10
申请号：US15197471
申请日：2016-06-29
申请人： Oracle International Corporation
发明人： Edward Alfonso Bucaro
IPC分类号： G06F17/00 , G06F12/06 , G06F13/40
CPC分类号： G06F12/0684 , G06F13/4068 , G06F2212/2532
摘要： Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board.

12. 发明授权

US09208075B2 Non-volatile memory device adapted to identify itself as a boot memory 有权
标题翻译：适用于将其自身识别为引导存储器的非易失性存储器件
公开(公告)号：US09208075B2
公开(公告)日：2015-12-08
申请号：US14176320
申请日：2014-02-10
申请人： Micron Technology, Inc.
发明人： Cliff Zitlaw , Frankie F. Roohparvar , David Eggleston
IPC分类号： G06F9/00 , G06F9/24 , G06F1/24 , G06F12/00 , G06F13/00 , G06F12/02 , G06F12/06 , G06F9/44 , G06F9/445
CPC分类号： G06F12/0246 , G06F9/4401 , G06F9/4403 , G06F9/4406 , G06F9/4408 , G06F9/445 , G06F12/0684
摘要： Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface.
摘要翻译：提供非易失性存储器件及其操作方法。一种这样的非易失性存储器件具有接口和控制电路。响应于在接口上接收询问请求，非易失性存储器设备适于将自身识别为引导存储器。

13. 发明申请

US20150262632A1 GROUPING STORAGE PORTS BASED ON DISTANCE 审中-公开
标题翻译：基于距离分组存储端口
公开(公告)号：US20150262632A1
公开(公告)日：2015-09-17
申请号：US14280564
申请日：2014-05-16
申请人： Fusion-io, Inc.
发明人： Lance Shelton , John Cagle
IPC分类号： G11C7/10 , G06F12/02
CPC分类号： G06F12/0284 , G06F12/0246 , G06F12/0684 , G06F2212/2542 , G11C7/1075 , G11C16/06 , G11C2207/108
摘要： Apparatuses, systems, methods, and computer program products are disclosed for grouping storage ports based on distance. A distance module may be configured to assign distance values to a plurality of ports. Distance values may be for data communications between a node and ports. A group module may be configured to assign one or more ports of a plurality of ports to one of a first port group and a second port group based on assigned distances. A selection module may be configured to select a second port group for data communications between a node and a non-volatile storage medium in response to a first port group being unavailable.
摘要翻译：公开了基于距离对存储端口进行分组的装置，系统，方法和计算机程序产品。距离模块可以被配置为将距离值分配给多个端口。距离值可以用于节点和端口之间的数据通信。组模块可以被配置为基于分配的距离将多个端口的一个或多个端口分配给第一端口组和第二端口组中的一个。选择模块可以被配置为响应于第一端口组不可用来选择用于节点和非易失性存储介质之间的数据通信的第二端口组。

14. 发明申请

US20150058559A1 NETWORK STORAGE SYSTEMS HAVING CLUSTERED RAIDS FOR IMPROVED REDUNDANCY AND LOAD BALANCING 有权
标题翻译：具有集群RAID的网络存储系统，用于改进冗余和负载均衡
公开(公告)号：US20150058559A1
公开(公告)日：2015-02-26
申请号：US14480273
申请日：2014-09-08
申请人： NetApp, Inc.
发明人： Mahmoud K. Jibbe , Abhishekh P. Sharma , Karthik Krishnamurthy Satchitanand , Venkata Ramprasad Darisa , Dhishankar Sengupta
IPC分类号： G06F3/06
CPC分类号： H04L67/1095 , G06F3/061 , G06F3/0619 , G06F3/065 , G06F3/0665 , G06F3/067 , G06F3/0689 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/2005 , G06F12/0684 , H04L45/22 , H04L45/30 , H04L67/1097
摘要： A clustered network-based storage system includes a host server, multiple high availability system controller pairs, and multiple storage devices across multiple arrays. Two independent storage array subsystems each include a quorum drive copy and are each controlled by a HA pair, with remote volume mirroring links coupling the separate HA pairs. The host server includes a virtualization agent that identifies and prioritizes communication paths, and also determines capacity across all system nodes. A system storage management agent determines an overall storage profile across the system. The virtualization agent, storage management agent, quorum drive copies and remote volume mirroring link all operate to provide increased redundancy, load sharing, or both between the separate first and second arrays of storage devices.
摘要翻译：基于群集的基于网络的存储系统包括主机服务器，多个高可用性系统控制器对以及跨多个阵列的多个存储设备。两个独立的存储阵列子系统各自包括仲裁驱动器副本，并且每个子系统都由HA对进行控制，远程卷镜像链接耦合单独的HA对。主机服务器包括一个识别和优先化通信路径的虚拟化代理，并确定所有系统节点的容量。系统存储管理代理确定整个系统的总体存储配置文件。虚拟化代理，存储管理代理，仲裁驱动器副本和远程卷镜像链接都可以在独立的第一和第二阵列存储设备之间提供增加的冗余，负载共享或两者。

15. 发明申请

US20150052316A1 CENTRALIZED MEMORY ALLOCATION WITH WRITE POINTER DRIFT CORRECTION 有权
标题翻译：具有写入点标签校正的集中存储器分配
公开(公告)号：US20150052316A1
公开(公告)日：2015-02-19
申请号：US14531448
申请日：2014-11-03
申请人： Juniper Networks, Inc.
发明人： Rami RAHIM , Pradeep S. Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：用于写入数据的系统包括存储器，至少一个存储器控制器和控制逻辑。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复并确定答复中的地址是否与包含在与其他存储器控制器相关联的应答中的地址相差阈值。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

16. 发明授权

US08812810B2 Memory control apparatus 有权
标题翻译：存储器控制装置
公开(公告)号：US08812810B2
公开(公告)日：2014-08-19
申请号：US12964566
申请日：2010-12-09
申请人： Akira Yoshida , Osamu Fujimoto , Hideyuki Ochi
发明人： Akira Yoshida , Osamu Fujimoto , Hideyuki Ochi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/00 , G06F9/24 , G06F15/177 , G06F12/06 , G06F12/02
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0646
摘要： A memory control apparatus includes: a plurality of setting output units each configured to output setting information for setting operation of each of a plurality of memory cells; and a plurality of selection units each configured to select operation or stop of the operation of each of the plurality of memory cells in accordance with the setting information.
摘要翻译：存储器控制装置包括：多个设置输出单元，每个设置输出单元被配置为输出用于设置多个存储器单元中的每一个的设置操作的设置信息; 以及多个选择单元，每个选择单元被配置为根据设置信息选择多个存储单元中的每一个的操作或停止操作。

17. 发明申请

US20120303925A1 METHOD AND DEVICE FOR CONFIGURING MEMORY CAPACITY 审中-公开
标题翻译：用于配置存储容量的方法和设备
公开(公告)号：US20120303925A1
公开(公告)日：2012-11-29
申请号：US13567273
申请日：2012-08-06
申请人： Zhikui HUANG , Yaobing Li , Jian Zhou
发明人： Zhikui HUANG , Yaobing Li , Jian Zhou
IPC分类号： G06F12/02
CPC分类号： G06F12/0684
摘要： The present invention discloses a method and a device for configuring memory capacity, which relates to the field of computer technologies, so as to solve the problem of complex operations of a method for configuring memory capacity in the prior art. A technical solution provided in an embodiment of the present invention includes: performing a first read/write operation on data in a first memory space; if a system status does not change during the first read/write operation, performing a second read/write operation on data in a second memory space obtained by updating the first memory space; if the system status changes during the first/second read/write operation, obtaining a memory address when the system status changes; and configuring the memory capacity according to the memory address. Embodiments of the present invention may be applied in an embedded system or a computer.
摘要翻译：本发明公开了一种用于配置存储器容量的方法和装置，其涉及计算机技术领域，以解决现有技术中用于配置存储器容量的方法的复杂操作的问题。本发明实施例提供的技术方案包括：对第一存储器空间中的数据执行第一读/写操作; 如果在所述第一读/写操作期间系统状态不改变，则对通过更新所述第一存储器空间获得的第二存储器空间中的数据执行第二读/写操作; 如果在第一/第二读/写操作期间系统状态改变，则当系统状态改变时获得存储器地址; 并根据存储器地址配置存储器容量。本发明的实施例可以应用于嵌入式系统或计算机。

18. 发明申请

US20120159025A1 Method and Device for Communication between a Master and a Number of Slaves According to a Serial Communication Protocol, in particular of the Open Drain Type 有权
标题翻译：根据串行通信协议，特别是开放式排放类型的主站和从站数量之间的通信的方法和设备
公开(公告)号：US20120159025A1
公开(公告)日：2012-06-21
申请号：US13326922
申请日：2011-12-15
申请人： François Tailliet
发明人： François Tailliet
IPC分类号： G06F13/00
CPC分类号： G06F13/4282 , G06F12/0684 , G06F13/4291 , G06F2213/0016 , G06F2213/0052 , H04L12/4135
摘要： According to one implementation, the slave identifier bits are tested recursively in groups of p bits. For these p bits, each slave will recognize, in its p corresponding identifier bits, one combination out of the 2p possible combinations. The slaves respond simultaneously (20) over the bus, for example an I2C bus, to a request from the master. The response is given by outputting a series of “1” bits in which each slave inserts a “0”, which is, for example, the priority logic value on the bus, the position of the “0” in the series of “1” bits being dependent on the binary value of the combination recognized by the slave in the group of p bits of its identifier. The master progressively determines on the fly, based on the bits of the frame received, the values of bits of these digital information items.
摘要翻译：根据一个实施方案，从标识符位以p位组递归地测试。对于这些p位，每个从器件将在其p个对应的标识符位中识别2p个可能组合中的一个组合。从站通过总线（20）同时响应主站的请求（20），例如I2C总线。通过输出一系列“1”位给出响应，其中每个从站插入“0”，例如，总线上的优先级逻辑值，“1”系列中的“0”位置 “位取决于从其在其标识符的p位组中识别的组合的二进制值。主设备基于所接收的帧的比特逐渐地确定这些数字信息项的比特值。

19. 发明授权

US08037239B2 Storage controller 有权
标题翻译：存储控制器
公开(公告)号：US08037239B2
公开(公告)日：2011-10-11
申请号：US11387968
申请日：2006-03-24
申请人： Ryoji Furuhashi
发明人： Ryoji Furuhashi
IPC分类号： G06F12/00
CPC分类号： G06F12/0684 , G06F3/0608 , G06F3/0613 , G06F3/0614 , G06F3/0631 , G06F3/0644 , G06F3/067
摘要： Provided is a storage controller that will not impair the operation of a storage control system even when a new storage area is added to a pool corresponding to an AOU volume. This storage controller includes a logical volume accessible by a host system; a pool associated with the logical volume and including one or more physical storage areas configuring a storage area of the logical volume; and a memory for storing attribute information showing an attribute of a physical storage area included in the pool; wherein the controller is configured to add a new physical storage area to the pool based on the attribute information.
摘要翻译：提供一种存储控制器，即使当将新的存储区域添加到对应于AOU卷的池中时，也不会影响存储控制系统的操作。该存储控制器包括由主机系统可访问的逻辑卷; 与所述逻辑卷相关联并且包括配置所述逻辑卷的存储区域的一个或多个物理存储区域的池; 以及存储器，用于存储表示包含在所述池中的物理存储区域的属性的属性信息; 其中所述控制器被配置为基于所述属性信息向所述池添加新的物理存储区域。

20. 发明授权

US07032158B2 System and method for recognizing and configuring devices embedded on memory modules 有权
公开(公告)号：US07032158B2
公开(公告)日：2006-04-18
申请号：US09840724
申请日：2001-04-23
申请人： Manuel J. Alvarez, II , Thomas A. Dye , Peter Geiger
发明人： Manuel J. Alvarez, II , Thomas A. Dye , Peter Geiger
IPC分类号： G11C29/00
CPC分类号： G06F9/4411 , G06F12/0607 , G06F12/0684 , G06F12/08 , G06F2212/401 , G11C7/20 , G11C2207/104
摘要： A method and system for identifying and configuring device-enhanced memory modules at system startup is described. A driver is described that performs a wakeup procedure at startup to identify installed device-enhanced memory modules, detect memory implementations such as interleaving and striping on memory modules, detect error detection and correction (ECC) implementations, and to configure the identified device-enhanced memory modules to use the detected implementations. The method may include several phases including, but not limited to, a start block phase, an ECC configuration phase, an ECC check phase, an interleave detect and configuration phase, a buffer check phase, and a final configuration phase. One or more of the phases may be performed at system startup and/or during normal system operation. Methods for shutting down and providing a sleep mode for device-enhanced memory modules are also described.

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