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11. 发明授权

US09535118B2 TAP addressable circuit with bi-directional TMS and second signal lead 有权
标题翻译：具有双向TMS和第二信号引线的TAP可寻址电路
公开(公告)号：US09535118B2
公开(公告)日：2017-01-03
申请号：US14853103
申请日：2015-09-14
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3183 , G01R31/3185 , G06F11/267
CPC分类号： G01R31/3172 , G01R31/31701 , G01R31/31705 , G01R31/31712 , G01R31/31713 , G01R31/31722 , G01R31/31727 , G01R31/3177 , G01R31/318364 , G01R31/318555 , G01R31/318558 , G06F11/267
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。

12. 发明申请

US20160003909A1 REDUCED SIGNALING INTERFACE METHOD & APPARATUS 审中-公开
公开(公告)号：US20160003909A1
公开(公告)日：2016-01-07
申请号：US14853103
申请日：2015-09-14
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/3172 , G01R31/31701 , G01R31/31705 , G01R31/31712 , G01R31/31713 , G01R31/31722 , G01R31/31727 , G01R31/3177 , G01R31/318364 , G01R31/318555 , G01R31/318558 , G06F11/267
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

13. 发明申请

US20140289577A1 SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT 有权
标题翻译：可选择的JTAG或跟踪数据存储和输出
公开(公告)号：US20140289577A1
公开(公告)日：2014-09-25
申请号：US14297051
申请日：2014-06-05
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/31723 , G01R31/31722 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318572 , G06F11/261 , G06F11/267 , G06F11/27 , G06F11/3466
摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
摘要翻译：地址和命令端口接口选择性地启用IC内的JTAG TAP域操作和跟踪域操作。端口在单个引脚上承载TMS和TDI输入和TDO输出，并在单独的引脚上接收时钟信号。可寻址的两个引脚接口将指令和数据加载并更新到IC内的TAP域。多个IC中的指令或数据更新操作同时发生。过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。标头位的逻辑电平用于启动，继续和停止向控制器传输数据。控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。

14. 发明授权

US08819510B2 Selectable JTAG or trace access with data store and output 有权
标题翻译：可选择的JTAG或跟踪访问，具有数据存储和输出
公开(公告)号：US08819510B2
公开(公告)日：2014-08-26
申请号：US14097738
申请日：2013-12-05
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177 , G06F11/26 , G06F11/34
CPC分类号： G01R31/31723 , G01R31/31722 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318572 , G06F11/261 , G06F11/267 , G06F11/27 , G06F11/3466
摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
摘要翻译：地址和命令端口接口选择性地启用IC内的JTAG TAP域操作和跟踪域操作。端口在单个引脚上承载TMS和TDI输入和TDO输出，并在单独的引脚上接收时钟信号。可寻址的两个引脚接口将指令和数据加载并更新到IC内的TAP域。多个IC中的指令或数据更新操作同时发生。过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。标头位的逻辑电平用于启动，继续和停止向控制器传输数据。控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。

15. 发明申请

US20130305110A1 REDUCED SIGNALING INTERFACE METHOD & APPARATUS 审中-公开
公开(公告)号：US20130305110A1
公开(公告)日：2013-11-14
申请号：US13941732
申请日：2013-07-15
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

16. 发明申请

US20130124935A1 REDUCED SIGNALING INTERFACE METHOD & APPARATUS 有权
公开(公告)号：US20130124935A1
公开(公告)日：2013-05-16
申请号：US13735545
申请日：2013-01-07
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

17. 发明申请

US20110291693A1 TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES 失效
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US20110291693A1
公开(公告)日：2011-12-01
申请号：US13206434
申请日：2011-08-09
申请人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： G01R31/26
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.
摘要翻译：用于测试半导体器件的方法，系统和设备。半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路，以及包括保险丝的熔丝电路，并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

18. 发明申请

US20110258506A1 REDUCED SIGNALING INTERFACE METHOD & APPARATUS 有权
标题翻译：减少信令接口方法和装置
公开(公告)号：US20110258506A1
公开(公告)日：2011-10-20
申请号：US13102742
申请日：2011-05-06
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。在本公开的第五方面中，一种接口选择电路，图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

19. 发明授权

US07954027B2 Reduced signaling interface method and apparatus 有权
公开(公告)号：US07954027B2
公开(公告)日：2011-05-31
申请号：US12952734
申请日：2010-11-23
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3172 , G01R31/31701 , G01R31/31705 , G01R31/31712 , G01R31/31713 , G01R31/31722 , G01R31/31727 , G01R31/3177 , G01R31/318364 , G01R31/318555 , G01R31/318558 , G06F11/267
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

20. 发明申请

US20110087938A1 REDUCED SIGNALING INTERFACE METHOD AND APPARATUS 有权
标题翻译：减少信号接口的方法和设备
公开(公告)号：US20110087938A1
公开(公告)日：2011-04-14
申请号：US12952734
申请日：2010-11-23
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G06F11/267
CPC分类号： G01R31/3172 , G01R31/31701 , G01R31/31705 , G01R31/31712 , G01R31/31713 , G01R31/31722 , G01R31/31727 , G01R31/3177 , G01R31/318364 , G01R31/318555 , G01R31/318558 , G06F11/267
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。

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