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11. 发明授权

US09245590B2 Stacked die flash memory device with serial peripheral interface 有权
标题翻译：具有串行外设接口的堆叠式闪存设备
公开(公告)号：US09245590B2
公开(公告)日：2016-01-26
申请号：US14194248
申请日：2014-02-28
申请人： Winbond Electronics Corporation
发明人： Hui Chen , Teng Su
IPC分类号： G11C16/10 , G11C5/06
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译：任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。支持堆叠模具的并行操作。

12. 发明授权

US09214211B2 Methods of and apparatus for determining unique die identifiers for multiple memory die within a common package 有权
标题翻译：用于在公共封装内确定多个存储器管芯的唯一管芯标识符的方法和装置
公开(公告)号：US09214211B2
公开(公告)日：2015-12-15
申请号：US14278962
申请日：2014-05-15
申请人： Winbond Electronics Corporation
发明人： Johnny Chan
IPC分类号： G06F3/00 , G11C8/18
CPC分类号： G11C8/18 , G11C16/20 , H01L2224/32145 , H01L2224/48145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.
摘要翻译：基于它们各自的唯一标识符（“UID”），通常将其打包为存储设备的多个存储器管芯确定各个管芯ID。外部控制器启动内部管芯ID（“DID”）确定过程，其中每个管芯在由其UID确定的多个时钟之后最终在其管芯上信令引脚上断言一个信号，并且基于在其自己的信令响应之前由其他死机断言的信号数。每个管芯在其自身的信令响应之前跟踪由另一个管芯所确定的信号的数量，以及可选地，信令引脚上的信号总数来确定器件的封装管芯数。

13. 发明申请

US20150346246A1 Method and Apparatus for Supply Voltage Glitch Detection in a Monolithic Integrated Circuit Device 有权
标题翻译：用于单片集成电路器件中电源电压毛刺检测的方法和装置
公开(公告)号：US20150346246A1
公开(公告)日：2015-12-03
申请号：US14293820
申请日：2014-06-02
申请人： Winbond Electronics Corporation
发明人： Nir Tasher , Valery Teper , Dennis Chin Cheng , Koying Huang
IPC分类号： G01R19/165 , G01R31/28
CPC分类号： G01R19/16552 , G01R19/16576 , G06F1/28 , G06F1/30
摘要： A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.
摘要翻译：单片集成电路器件可以包括用于检测不正确的电源电压条件的电源电压毛刺检测器。有利地，电源电压毛刺检测器的检测阈值是基于设备的操作模式或设备的特定部分的操作模式而自适应地设置的，该设备的设备内部基于设备接收到的某些输入，诸如命令，中断，控制信号等等。

14. 发明申请

US20150248921A1 Stacked Die Flash Memory Device With Serial Peripheral Interface 有权
标题翻译：具有串行外设接口的堆叠模组闪存器件
公开(公告)号：US20150248921A1
公开(公告)日：2015-09-03
申请号：US14194248
申请日：2014-02-28
申请人： Winbond Electronics Corporation
发明人： Hui Chen , Teng Su
IPC分类号： G11C5/06 , G11C16/10
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译：任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。支持堆叠模具的并行操作。

15. 发明申请

US20140328126A1 Flash Memory Having Dual Supply Operation 有权
标题翻译：具有双电源供电操作的闪存
公开(公告)号：US20140328126A1
公开(公告)日：2014-11-06
申请号：US13875760
申请日：2013-05-02
申请人： WINBOND ELECTRONICS CORPORATION
发明人： Jongjun Kim , Eungjoon Park
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C16/12 , G11C16/28 , G11C29/82
摘要： A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
摘要翻译：闪存器件可以从两个电源电压操作，一个从外部提供，另一个从外部电源电压在闪存器件内产生。闪存器件可以设置有用于与低电源电压或高电源电压集成电路接口的可选级缓冲器。为了提供更大的灵活性，闪存器件可以具有从外部源接收第二电源电压的能力，其可以优先于内部产生的第二电源电压，或者可以与内部产生的第二电源电压。

16. 发明申请

US20140036596A1 Sense Amplifier for Flash Memory 有权
标题翻译：闪存感应放大器
公开(公告)号：US20140036596A1
公开(公告)日：2014-02-06
申请号：US13563337
申请日：2012-07-31
申请人： Johnny Chan , Koying Huang
发明人： Johnny Chan , Koying Huang
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642
摘要： A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.
摘要翻译：读出放大器具有参考单元电流分支，其中参考单元确定参考单元电流，列负载将参考单元电流转换为参考电压，以及反馈电路以维持参考单元漏极电压。读出放大器还具有主单元电流分支，其中从闪存单元阵列操作选择的主单元确定主单元电流，列负载将主单元电流转换为主电压，以及反馈电路，以维持主电池漏极电压。差分放大器将参考电压与主电压进行比较，并根据相对值在其输出端提供逻辑电平。升压电路具有耦合在列负载上的上拉部分和耦合在主单元两端的下拉部分，用于加速逻辑零检测时间。

17. 发明授权

US07788483B1 Method and apparatus of identifying and enabling of functions of a trusted platform module device 有权
标题翻译：识别和启用可信平台模块设备功能的方法和装置
公开(公告)号：US07788483B1
公开(公告)日：2010-08-31
申请号：US11124917
申请日：2005-05-09
申请人： Ohad Falik , Dan Morav
发明人： Ohad Falik , Dan Morav
IPC分类号： H04L29/06
CPC分类号： H04L63/061 , H04L9/3263 , H04L63/0823 , H04L2209/127 , H04L2209/56
摘要： A method is disclosed for a certifying authority (CA) to establish a secure status and authenticity in an integrated circuit (IC). Cryptographic logic and certification logic are incorporated in the IC by an IC manufacturer. The cryptographic logic is operable to generate a cryptographic key intended to be communicated external to the IC. The certification logic includes a certification key intended for use in establishing a secure certification arrangement. The certification key is communicated securely to the CA and a secure certification arrangement is established between the CA and the IC using the certification key. During the secure certification arrangement, the cryptographic key is accessed by the CA to certify the cryptographic key associated with the IC and in response thereto the certification key is deleted and the secured certification arrangement is terminated.
摘要翻译：公开了一种用于认证机构（CA）在集成电路（IC）中建立安全状态和真实性的方法。加密逻辑和认证逻辑由IC制造商纳入IC。加密逻辑可操作以产生旨在在IC外部通信的加密密钥。认证逻辑包括旨在用于建立安全认证安排的认证密钥。证书密钥安全地传送给CA，并且使用认证密钥在CA和IC之间建立安全的认证安排。在安全认证安排期间，加密密钥由CA访问以证明与IC相关联的加密密钥，并且响应于此，认证密钥被删除并且安全证书安排被终止。

18. 发明申请

US20090169188A1 Apparatus and method for fan auto-detection 有权
标题翻译：风扇自动检测装置及方法
公开(公告)号：US20090169188A1
公开(公告)日：2009-07-02
申请号：US12003825
申请日：2008-01-02
申请人： Shih-Feng Huang , Chia-Ching Lu , Ming-Che Hung
发明人： Shih-Feng Huang , Chia-Ching Lu , Ming-Che Hung
IPC分类号： H02P7/29
CPC分类号： H05K7/20209 , Y10S388/934
摘要： An apparatus for detecting a type of fan and controlling the fan, the fan providing during operation a tachometer signal indicating a speed of the fan, the apparatus includes: a direct current (DC) generator for coupling to the fan and configured to provide a first voltage to the fan; a resistor for providing, while the DC generator provides the first voltage, a sensed voltage relating to the type of the fan, wherein the resistor is connected to a reference voltage and for coupling to a pulse-width modulation (PWM) control terminal of the fan; an input judgment component coupled to the resistor to receive the sensed voltage, the input judgment component being configured to determine whether the fan is a 4-wire PWM fan with an internal pull-up resistor based on the sensed voltage and to provide a judgment signal indicating the determination; a PWM generator coupled to the input judgment component to receive the judgment signal, the PWM generator being configured to provide to the fan a PWM control signal to control the fan if the judgment signal indicates that the fan is the 4-wire PWM fan with an internal pull-up resistor; and a tachometer coupled to the DC generator and the PWM generator, the tachometer being configured to receive the tachometer signal to detect a change in the speed of the fan.
摘要翻译：一种用于检测风扇类型并控制风扇的装置，风扇在运行期间提供表示风扇速度的转速表信号，该装置包括：直流（DC）发生器，用于耦合到风扇并且被配置为提供第一风扇电压; 电阻，用于在DC发生器提供第一电压时提供与风扇类型相关的感测电压，其中电阻器连接到参考电压并用于耦合到脉冲宽度调制（PWM）控制端子风扇; 输入判断部件，耦合到所述电阻器以接收感测的电压，所述输入判断部件被配置为基于所感测的电压来确定所述风扇是具有内部上拉电阻器的4线PWM风扇，并且提供判断信号表明确定; PWM发生器，其耦合到所述输入判断部件以接收所述判断信号，所述PWM发生器被配置为向所述风扇提供PWM控制信号以控制所述风扇，如果所述判断信号指示所述风扇是具有内部上拉电阻; 以及耦合到所述DC发生器和所述PWM发生器的转速计，所述转速计被配置为接收所述转速计信号以检测所述风扇的速度的变化。

19. 发明申请

US20080310655A1 PROGRAMMABLE INTEGRATED MICROPHONE INTERFACE CIRCUIT 有权
标题翻译：可编程集成麦克风接口电路
公开(公告)号：US20080310655A1
公开(公告)日：2008-12-18
申请号：US11761957
申请日：2007-06-12
申请人： PETER HOLZMANN
发明人： PETER HOLZMANN
IPC分类号： H04R3/00
CPC分类号： H04R3/00 , H04R19/016
摘要： An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. In an embodiment, the integrated circuit includes a bias circuit, an amplifier circuit and two feedback circuits. The amplifier circuit includes a first input, a second input, and an output. The first input receives either the input signal or a feedback signal, depending upon mode control signals. The second input receives either the feedback signal or the input signal depending upon the mode control signals. The first feedback circuit is in communication with the output and the first input of the amplifier and includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit and provides the feedback signal. The mode control signals can be set in a programmable mode control register.
摘要翻译：用于提供可编程麦克风接口的集成电路包括用于接收输入信号的输入端和用于提供输出音频信号的输出端。在一个实施例中，集成电路包括偏置电路，放大器电路和两个反馈电路。放大器电路包括第一输入，第二输入和输出。根据模式控制信号，第一输入接收输入信号或反馈信号。根据模式控制信号，第二输入接收反馈信号或输入信号。第一反馈电路与放大器的输出和第一输入端通信，并且包括并联连接的第一电阻器和第一电容器。第二反馈电路包括积分器电路并提供反馈信号。模式控制信号可以在可编程模式控制寄存器中设置。

20. 发明申请

US20080101453A1 Digital pulse width modulation with variable period and error distribution 有权
标题翻译：具有可变周期和误差分布的数字脉宽调制
公开(公告)号：US20080101453A1
公开(公告)日：2008-05-01
申请号：US11591114
申请日：2006-10-31
申请人： Samuel Chi Hong Yau
发明人： Samuel Chi Hong Yau
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03F3/217 , H03F2200/348 , H03F2200/351
摘要： Digital pulse width modulation with variable period and error distribution that improves the tradeoff between resolution and clock speed in pulse width modulation circuits so that a higher resolution can be achieved with a lower clock speed. A preferred method includes, for a signal sample S and each value of P in a range Pmin to Pmax of pulse periods P, determining a pulse width V=round(P*S), where round(P*S) is the closest integer value of P*S, and the magnitude of the error |E|=|S−V/P|, for the value of V (Vopt) and P (Popt) associated with the lowest value of the magnitude of the error |E|, providing an output pulse of a pulse width Vopt during the pulse period Popt, and successively repeating a) and b). Other aspects of the invention may include error distribution, error squelching to prevent idle-tone, idle-noise artifacts, 2-samples-per-pulse and non-uniform sampling and pulsing. Other features are disclosed.
摘要翻译：具有可变周期和误差分布的数字脉宽调制改善了脉冲宽度调制电路中分辨率和时钟速度之间的权衡，从而可以以更低的时钟速度实现更高的分辨率。对于信号样本S和在脉冲周期P的范围Pmin至Pmax的P的每个值，优选的方法包括：确定脉冲宽度V = round（P * S），其中round（P * S）是最接近的整数对于与误差幅度E |的最小值相关联的V（Vopt）和P（Popt）的值，P * S的值，以及误差的幅度| E | = | SV / P | 在脉冲周期Popt期间提供脉冲宽度Vopt的输出脉冲，并连续重复a）和b）。本发明的其他方面可以包括误差分布，误差压缩以防止空闲音，空闲噪声伪像，每脉冲2-样本和非均匀采样和脉冲。公开了其他特征。

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