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11. 发明授权

US10624200B2 Undulator 有权
公开(公告)号：US10624200B2
公开(公告)日：2020-04-14
申请号：US15527447
申请日：2015-11-13
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： Shan Qiao , Rui Chang , Fuhao Ji , Mao Ye
IPC分类号： H01F7/02 , H05H7/04 , G21K1/00 , H05H13/04
CPC分类号： H05H7/04 , G21K1/003 , H01F7/02 , H01F7/0278 , H05H13/04 , H05H2007/041
摘要： An undulator comprises at least M permanent magnet periods arranged sequentially in a transmission direction of electron beams, each of the permanent magnet periods comprises four rows of permanent magnet structures, in which each row comprises N rows of permanent magnet groups, and each row of the permanent magnet groups comprises K permanent magnet units, wherein M, N and K are natural numbers greater than or equal to 1; the four rows of the permanent magnet structures are pairwise matched, then relatively disposed on both sides of the transmission direction of electron beams, and are capable of forming at least one composite magnetic fields by relative displacement, such that elliptically polarized light, circularly polarized light, or linearly polarized light with an arbitrary polarization angle of 0°˜360° is generated when electron beams pass through the composite magnetic fields, and such that velocity directions of electrons are deviated from an axis direction of the undulator.

12. 发明申请

US20190094128A1 METHOD FOR ADJUSTING AND CONTROLLING BOUNDARY OF GRAPHENE 审中-公开
公开(公告)号：US20190094128A1
公开(公告)日：2019-03-28
申请号：US15990777
申请日：2018-05-28
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADAMY OF SCIENCES
发明人： HAOMIN WANG , LINGXIU CHEN , LI HE , HUISHAN WANG , HONG XIE , XIUJUN WANG , XIAOMING XIE
IPC分类号： G01N21/17 , B82Y40/00 , C01B32/182
摘要： A method for adjusting and controlling a boundary of graphene, comprising: providing an insulating substrate and placing the insulating substrate in a growth chamber; and feeding first reaction gas into the growth chamber, the first reaction gas at least comprising carbon source gas, and controlling a flow rate of the first reaction gas to forming a graphene structure having a first boundary shape on a surface of the insulating substrate through controlling a flow rate of the first reaction gas. The present invention realizes the controllability of the boundary of the graphene by adjusting the ratio of the carbon source gas to catalytic gas in the growth process of graphene on the surface of the substrate; the present invention can enable graphene to sequentially continuously grow by changing growth conditions on the basis of already formed graphene, so as to change the original boundary shape of the graphene.

13. 发明申请

US20180002831A1 GROWTH METHOD OF GRAPHENE 有权
公开(公告)号：US20180002831A1
公开(公告)日：2018-01-04
申请号：US14762012
申请日：2015-03-26
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： HAOMIN WANG , SHUJIE TANG , GUANGYUAN LU , TIANRU WU , DA JIANG , GUQIAO DING , XUEFU ZHANG , HONG XIE , XIAOMING XIE , MIANHENG JIANG
IPC分类号： C30B25/20 , C30B23/02 , C23C16/50 , C23C16/26 , C23C14/28 , C30B29/02 , C23C14/06
CPC分类号： C30B25/205 , C23C14/0605 , C23C14/28 , C23C16/26 , C23C16/50 , C30B23/00 , C30B23/025 , C30B25/00 , C30B29/02
摘要： The present invention provides a growth method of grapheme, which at least comprises the following steps: S1: providing an insulating substrate, placing the insulating substrate in a growth chamber; S2: heating the insulating substrate to a preset temperature, and introducing a gas containing catalytic element into the growth chamber; S3: feeding carbon source into the growth chamber and growing a graphene thin film on the insulating substrate. The present invention adopts a catalytic manner of introducing catalytic element, and rapid grows a high quality graphene on the insulating substrate, which avoids the transition process of the graphene, enables to improve the production yield of the graphene, reduces the growth cost of the graphene, and thus the mass production can be facilitated. The graphene grown by the present invention may be applied in the field of novel graphene electronic devices, graphene transparent conducting film, transparent conducting coating and the like.

14. 发明申请

US20170362463A1 METHOD FOR PREPARING AN ALUMINUM OXIDE POLISHING SOLUTION 审中-公开
公开(公告)号：US20170362463A1
公开(公告)日：2017-12-21
申请号：US15219540
申请日：2016-07-26
申请人： Shanghai Xinanna Electronic Technology Co., LTD , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Weilei Wang , Weili Liu , Zhitang Song
IPC分类号： C09G1/02 , C09K3/14
CPC分类号： C09G1/02 , C09K3/1436
摘要： The present disclosure provides a method for preparing an aluminum oxide polishing solution. The methods include: 1) mixing a silane coupling agent, ethyl alcohol, and water to form a hydrolysate; 2) under a condition of heating and stirring at a temperature between 95° C. and 110° C., adding the hydrolysate into aluminum oxide powder; keeping stirring while heating till liquid is completely volatilized, thereby obtaining a modified aluminum oxide; 3) grinding the modified aluminum oxide into powder and dispersing the powder into water; adjusting solution pH to 9.5-10.5, thereby obtaining the aluminum oxide polishing solution. It may achieve a polishing efficiency of pH=13.00 by using the aluminum oxide polishing solution of the present disclosure; meanwhile, less scratches will occur to a polishing disc.

15. 发明申请

US20170233589A1 FILM-FORMING SILICA SOL, METHOD OF PREPARING THE SAME, AND APPLICATION OF THE SAME 审中-公开
公开(公告)号：US20170233589A1
公开(公告)日：2017-08-17
申请号：US15219522
申请日：2016-07-26
申请人： Yongxia Wang , Weili Liu , Zhitang Song
发明人： Yongxia Wang , Weili Liu , Zhitang Song
IPC分类号： C09D7/12 , C09D125/14 , B05D7/14 , C09D175/04
CPC分类号： C09D7/61 , B05D7/14 , C08K3/36 , C09D1/00 , C09D125/14 , C09D175/04
摘要： The present disclosure relates to the field of preparing an inorganic nanometer material and application thereof, and specifically relates to a film-forming silica sol, a method of preparing the silica sol, and usage thereof. The present disclosure provides a film-forming silica sol comprising, by weight percentage, constituents of: silica sol: 66-91%; modifying agent: 0.1-1.8%; film-forming auxiliary: 7.2-33.9%. The present disclosure further provides a method of preparing a film-forming silica sol and an application thereof. With the film-forming silica sol, a method of preparing the silica sol, and usage thereof according to the present disclosure, the prepared film-forming silica sol has a good appearance transparency and stability, and when applied to paint as a film-forming coating, it has a good glossiness, a high hardness, and a strong adhesive force; therefore, it has a high practical value in the paint field.

16. 发明申请

US20170084814A1 Nano-scale Superconducting Quantum Interference Device and Manufacturing Method thereof 有权
公开(公告)号：US20170084814A1
公开(公告)日：2017-03-23
申请号：US15124668
申请日：2014-04-08
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： LEI CHEN , ZHEN WANG
IPC分类号： H01L39/22 , H01L39/24 , H01L29/06
CPC分类号： H01L39/223 , H01L29/0676 , H01L39/2406 , H01L39/2416 , H01L39/2493
摘要： A nano-scale superconducting quantum interference device and a manufacturing method thereof, comprising the following steps of: S1: providing a substrate and growing a first superconducting material layer thereon; S2: forming a photo-resist layer and performing patterning; S3: etching the first superconducting material layer in a predetermined region; S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3; S5: growing a second superconducting material layer; S6: removing the structure above the plane where the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted; S7: forming at least one nanowire vertical to the insulating interlayer, to obtain the nano-scale superconducting quantum interference device. The width of the superconducting ring and the length of the nano junction are determined by the insulating interlayer.

17. 发明授权

US09601337B2 Manufacturing method of graphene modulated high-K oxide and metal gate MOS device 有权
公开(公告)号：US09601337B2
公开(公告)日：2017-03-21
申请号：US14423234
申请日：2014-02-21
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： Zengfeng Di , Xiaohu Zheng , Gang Wang , Miao Zhang , Xi Wang
IPC分类号： H01L21/66 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/16 , H01L21/02 , H01L21/265 , H01L21/285 , H01L21/324 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28255 , H01L21/02115 , H01L21/02181 , H01L21/02252 , H01L21/02271 , H01L21/0228 , H01L21/02315 , H01L21/02321 , H01L21/0234 , H01L21/02381 , H01L21/26513 , H01L21/2855 , H01L21/324 , H01L22/14 , H01L29/16 , H01L29/1606 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/66431 , H01L29/66477 , H01L29/6659 , H01L29/7781 , H01L29/7833
摘要： A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved. The fluorinated graphene can enable the graphene to become a high-quality insulator on the basis of keeping the excellent property of the graphene, so that the influence thereof on the electrical property of the Ge-based device is reduced. By adopting the ozone plasmas to treat the Ge-based graphene and then by adopting the atomic layer deposition technology, an ultrathin Hf-based high-k gate dielectric layer can be obtained.

18. 发明申请

US20160260604A1 PREPARATION METHOD OF GRAPHENE NANORIBBON ON h-BN 有权
标题翻译：石墨纳米粒在h-BN上的制备方法
公开(公告)号：US20160260604A1
公开(公告)日：2016-09-08
申请号：US14803371
申请日：2015-07-20
申请人： SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： HAOMIN WANG , LI HE , LINGXIU CHEN , HONG XIE , HUISHAN WANG , SHUJIE TANG , LEI LI , DAOLI ZHANG , XIAOMING XIE , MIANHENG JIANG
IPC分类号： H01L21/02 , H01L21/311
CPC分类号： H01L21/02527 , C01B32/182 , C01B2204/06 , H01L21/02389 , H01L21/0243 , H01L21/0259 , H01L21/0262 , H01L21/02658
摘要： A preparation method of a graphene nanoribbon on h-BN, comprising: 1) forming a h-BN groove template with a nano ribbon-shaped groove structure on the h-BN by adopting a metal catalysis etching method; 2) growing a graphene nanoribbon in the h-BN groove template by adopting a chemical vapor deposition method. In the present invention, a CVD method is adopted to directly prepare a morphology controllable graphene nanoribbon on the h-BN, which helps to solve the long-term critical problem that the graphene is difficult to nucleate and grow on an insulating substrate, and to avoid the series of problems introduced by the complicated processes of the transferring of the graphene and the subsequent clipping manufacturing for a nanoribbon and the like.
摘要翻译：一种h-BN上石墨烯纳米棒的制备方法，包括：1）采用金属催化蚀刻法在h-BN上形成具有纳米带状凹槽结构的h-BN凹槽模板; 2）采用化学气相沉积法在h-BN槽模板中生长石墨烯纳米棒。在本发明中，采用CVD方法在h-BN上直接制备形态可控的石墨烯纳米棒，这有助于解决石墨烯难以在绝缘基板上成核和生长的长期关键问题，并且避免了由石墨烯转移的复杂过程引起的一系列问题以及随后的纳米棒等的制造。

19. 发明申请

US20140199825A1 SILICON-GERMANIUM HETEROJUNCTION TUNNEL FIELD EFFECT TRANSISTOR AND PREPARATION METHOD THEREOF 有权
标题翻译：硅锗绝缘隧道场效应晶体管及其制备方法
公开(公告)号：US20140199825A1
公开(公告)日：2014-07-17
申请号：US13811268
申请日：2012-09-19
申请人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
发明人： Jiantao Bian , Zhongying Xue , Zengfeng Di , Miao Zhang
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L21/02532 , H01L21/02617 , H01L29/165 , H01L29/66356 , H01L29/66431 , H01L29/7391
摘要： A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production.
摘要翻译：提供硅/锗（SiGe）异质结隧道场效应晶体管（TFET）及其制备方法，其中器件的源极区域在硅锗（GeGe）或Ge区域上制造，漏极区域在Si区域中制造器件，从而在确保低OFF状态电流的同时获得高导通状态电流。本地Ge氧化和浓缩技术用于在某些地区实施高Ge含量的硅锗绝缘体（SGOI）或锗绝缘体（GOI）。在高Ge含量的SGOI或GOI中，Ge含量可控制在50％〜100％之间。另外，膜厚可以从5nm到20nm的范围内控制，便于实现器件工艺。在SiGe或Ge和Si的氧化和浓缩过程中，在SiGe或Ge和Si之间形成具有梯度Ge含量的SiGe异质结结构，从而消除缺陷。根据本发明的制备方法具有与CMOS工艺兼容的简单工艺，并且适用于大规模工业生产。

20. 发明申请

US20130054210A1 Method for Determining BSIMSOI4 DC Model Parameters 有权
标题翻译：确定BSIMSOI4直流模型参数的方法
公开(公告)号：US20130054210A1
公开(公告)日：2013-02-28
申请号：US13696455
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06F17/10
CPC分类号： G01R31/2628 , G01R31/2603 , G06F17/5036
摘要： The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.
摘要翻译：本发明提供了一种用于确定BSIMSOI4直流（DC）模型参数的方法，其中，体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管（MOSFET）器件和多个MOSFET器件提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp，Id / Ip-Vd-Vg，Ig-Vg-Vd，Ig-Vp，Ip-Vg-vd，Is / Id-Vp和Id / Ip-Vp-Vd特性测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp，Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。在本发明中，根据模型方程依次选择适当的试验曲线，并连续确定各种参数，从而准确有效地提取BSIMSOI4型号的直流参数。

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