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11. 发明申请

US20120250441A1 Separate Pass Gate Controlled Sense Amplifier 有权
标题翻译：独立通道门控感应放大器
公开(公告)号：US20120250441A1
公开(公告)日：2012-10-04
申请号：US13077798
申请日：2011-03-31
申请人： Richard S. Roy , Dipak K. Sikdar
发明人： Richard S. Roy , Dipak K. Sikdar
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C11/4091 , G11C2207/005
摘要： A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.
摘要翻译：存储器系统，其包括耦合到第一组动态随机存取存储器（DRAM）单元的第一位线，耦合到第二组DRAM单元的第二（互补）位线以及耦合到第一和第二位线。感测放大器包括耦合在第一和第二位线之间的一对交叉耦合的反相器（或类似的锁存电路）以及将第一位线耦合到第一全局位线的第一选择晶体管和第二选择晶体管将第二位线耦合到第二全局位线。独立地控制第一和第二选择晶体管，由此能够实现改进的读和写访问序列，从而消除与位线耦合相关联的信号损耗，消除读取凸起条件，并消除后期写入条件。

12. 发明授权

US08238169B2 Method and apparatus for restoring data in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中恢复数据的方法和装置
公开(公告)号：US08238169B2
公开(公告)日：2012-08-07
申请号：US13027621
申请日：2011-02-15
申请人： Jeong Y. Choi , Stephen Fung
发明人： Jeong Y. Choi , Stephen Fung
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G06F11/1068 , G11C2029/0411
摘要： A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data.
摘要翻译：一种用于基于故障类型选择性地恢复非易失性存储器阵列中的数据的方法和装置。通过执行特定存储器部分的两个读数来识别弱数据和错误数据。或者，在首次读取数据之后使用纠错码来识别错误数据。数据恢复的方式取决于数据是否因擦除故障或程序故障而改变。如果仅发生程序故障，则数据将被重新编程，而无需中间擦除步骤。如果数据经历擦除故障，则在使用正确的数据编程之前，数据将被擦除。

13. 发明授权

US08161355B2 Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process 有权
标题翻译：自动刷新，以提高标准CMOS逻辑过程中嵌入式非易失性存储器的数据保留和耐久性
公开(公告)号：US08161355B2
公开(公告)日：2012-04-17
申请号：US12378249
申请日：2009-02-11
申请人： Stephen Fung , Vithal Rao , Da-Guang Yu , J. Eric Ruetz , Chee T. Chua , Jawji Chen , Kameswara K. Rao
发明人： Stephen Fung , Vithal Rao , Da-Guang Yu , J. Eric Ruetz , Chee T. Chua , Jawji Chen , Kameswara K. Rao
IPC分类号： G11C29/00
CPC分类号： G11C16/3431 , G06F11/1068 , G11C16/10 , G11C29/52 , G11C2029/0411 , H03M13/19
摘要： A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
摘要翻译：一种用于基于由纠错码检测到的故障类型来选择性地刷新非易失性存储器阵列中的数据的方法。如果页面被确定为无错误，则不会进行刷新操作。否则，如果页面上的单个错误字含有擦除和编程的位错误，则会执行由擦除和程序组成的刷新操作。如果页面上的单个错误单词仅包含程序故障，则会擦除擦除操作。

14. 发明申请

US20120068339A1 VLSI Package for High Performance Integrated Circuit 审中-公开
标题翻译：用于高性能集成电路的VLSI封装
公开(公告)号：US20120068339A1
公开(公告)日：2012-03-22
申请号：US12887298
申请日：2010-09-21
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/50 , G11C5/02 , H01L23/49838 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate.
摘要翻译：提供封装的集成电路用于放置在提供电力线和数据访问通道的印刷电路板（PCB）层上。封装的集成电路包括：具有数据通道和电源线的封装基板; 具有功能部件的电路基板，其中（a）封装基板中的电源线和数据通道通过传导凸块而耦合到基板的功能部件，（b）将PCB中的数据访问通道耦合到的导电球到封装衬底中的数据通道沿封装衬底的边缘定位; 和（c）将PCB中的电力线和封装衬底中的电力线耦合的导电球位于封装衬底的内部。此外，集成电路还可以包括具有有源部件的电路基板，在基板的中心部分包括SerDes电路。

15. 发明授权

US08139399B2 Multiple cycle memory write completion 有权
标题翻译：多周期内存写入完成
公开(公告)号：US08139399B2
公开(公告)日：2012-03-20
申请号：US12577994
申请日：2009-10-13
申请人： Richard S. Roy
发明人： Richard S. Roy
IPC分类号： G11C11/24 , G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/1015 , G11C11/406 , G11C11/40618 , G11C2207/229
摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.
摘要翻译：一种通过执行不完整的写操作来减少存储器单元的存储器周期时间的存储器系统。在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

16. 发明申请

US20120025397A1 Semiconductor Chip Layout 有权
标题翻译：半导体芯片布局
公开(公告)号：US20120025397A1
公开(公告)日：2012-02-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

17. 发明申请

US20100208530A1 Two Bits Per Cell Non-Volatile Memory Architecture 失效
标题翻译：每个单元非易失性存储器架构的两个位
公开(公告)号：US20100208530A1
公开(公告)日：2010-08-19
申请号：US12370718
申请日：2009-02-13
申请人： Chee T. Chua , Kameswara K. Rao , Vithal R. Rao , Jawji Chen , Da-Guang Yu , J. Eric Ruetz , Stephen Fung
发明人： Chee T. Chua , Kameswara K. Rao , Vithal R. Rao , Jawji Chen , Da-Guang Yu , J. Eric Ruetz , Stephen Fung
IPC分类号： G11C7/00
CPC分类号： G11C16/0441
摘要： A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.
摘要翻译：用于保存单个二进制值的存储器电路。第一位单元保持逻辑高值和逻辑低值中的一个，并且第二位单元也保持逻辑高值和逻辑低值中的一个。提供电路，用于当存储器电路中的二进制值为逻辑高值时，将逻辑高值放置在第一位单元中，并且提供电路用于当第二位单元中的二进制值存储器电路将成为逻辑低电平值。以这种方式，存储器电路内存在逻辑高值，存储器电路内的单个二进制值是逻辑高值还是逻辑低值。二进制值的两个值之间的差异是两个位单元中哪一个保持逻辑高值。因此，可以在不使用读出放大器的情况下感测该存储器电路。

18. 发明申请

US20100205504A1 Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process 有权
标题翻译：自动刷新，以提高标准CMOS逻辑过程中嵌入式非易失性存储器的数据保留和耐久性
公开(公告)号：US20100205504A1
公开(公告)日：2010-08-12
申请号：US12378249
申请日：2009-02-11
申请人： Stephen Fung , Vithal Rao , Da-Guang Yu , J. Eric Ruetz , Chee T. Chua , Jawji Chen , Kameswara K. Rao
发明人： Stephen Fung , Vithal Rao , Da-Guang Yu , J. Eric Ruetz , Chee T. Chua , Jawji Chen , Kameswara K. Rao
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C16/3431 , G06F11/1068 , G11C16/10 , G11C29/52 , G11C2029/0411 , H03M13/19
摘要： A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
摘要翻译：一种用于基于由纠错码检测到的故障类型来选择性地刷新非易失性存储器阵列中的数据的方法。如果页面被确定为无错误，则不会进行刷新操作。否则，如果页面上的单个错误字含有擦除和编程的位错误，则会执行由擦除和程序组成的刷新操作。如果页面上的单个错误单词仅包含程序故障，则会擦除擦除操作。

19. 发明授权

US07353438B2 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US07353438B2
公开(公告)日：2008-04-01
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储器系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

20. 发明授权

US10050773B1 Bootstrapped autonegotiation clock from a referenceless clock chip 有权
公开(公告)号：US10050773B1
公开(公告)日：2018-08-14
申请号：US15199979
申请日：2016-06-30
申请人： MoSys, Inc.
发明人： Scott A Irwin , Charles W Boecker
IPC分类号： H04L7/00 , H04L7/033 , H04L7/027 , H03L7/08
摘要： A method, system and apparatus, for bootstrapping an autonegotiation signal in an intermediate device. The intermediate device initializes using a referenceless clock circuit. The intermediate device then recovers a more accurate clock sourced from a second device via a clock data recovery circuit in the intermediate device. The second device has a physical medium attachment interface within the intermediate device that does not require autonegotiation. The autonegotiation signal is communicated to a first device having a physical medium dependent interface to the intermediate device, thus requiring autonegotiation.

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