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11. 发明申请

US20120095361A1 MULTI-CHANNEL BIOPOTENTIAL SIGNAL ACQUISITION SYSTEMS 有权
标题翻译：多通道生物信号获取系统
公开(公告)号：US20120095361A1
公开(公告)日：2012-04-19
申请号：US13227316
申请日：2011-09-07
申请人： Jiawei XU , Refet Firat Yazicioglu
发明人： Jiawei XU , Refet Firat Yazicioglu
IPC分类号： A61B5/053 , A61B5/04
CPC分类号： A61B5/04004 , A61B5/0428 , H03F3/45475 , H03F3/45928 , H03F2200/261 , H03F2203/45138
摘要： A multi-channel biopotential signal acquisition system is disclosed. In the system, a plurality of biopotential channels is corrected for common-mode interference. In one aspect, each biopotential channel includes an electrode for providing a biopotential input signal and an associated amplifier for amplifying the biopotential input signal and providing a biopotential output signal. The output signal is processed in a processor. Each biopotential output signal is passed to a common-mode feedback system, which determines an average common-mode signal and feeds that signal back to each of the amplifiers in each of the biopotential channels to enhance common-mode rejection ratio of the system.
摘要翻译：公开了一种多通道生物电势信号采集系统。在该系统中，针对共模干扰来校正多个生物电势通道。在一个方面，每个生物电位通道包括用于提供生物电位输入信号的电极和用于放大生物电位输入信号并提供生物电位输出信号的相关放大器。在处理器中处理输出信号。每个生物电势输出信号被传递到共模反馈系统，该共模反馈系统确定平均共模信号，并将该信号反馈给每个生物电位通道中的每个放大器，以增强系统的共模抑制比。

12. 发明申请

US20120063252A1 VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION 有权
标题翻译：具有降低能源消耗的可变性感应放大器
公开(公告)号：US20120063252A1
公开(公告)日：2012-03-15
申请号：US13231706
申请日：2011-09-13
申请人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryam Ashouei , Jos Huisken
发明人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryam Ashouei , Jos Huisken
IPC分类号： H03F3/45 , G11C7/02
CPC分类号： G11C11/413 , G11C7/06 , G11C7/065 , G11C7/08
摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.
摘要翻译：公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活第一和第二放大器。第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

13. 发明申请

US20120063211A1 METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY 审中-公开
标题翻译：改进SRAM存储器可写性的方法
公开(公告)号：US20120063211A1
公开(公告)日：2012-03-15
申请号：US13231727
申请日：2011-09-13
申请人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryan Ashouei , Jos Huisken
发明人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryan Ashouei , Jos Huisken
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/06 , G11C7/065 , G11C7/08
摘要： A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.
摘要翻译：公开了一种提高SRAM单元可写性的方法。一方面，该方法包括将高于全局接地电压的第一电压和高于全局电源电压的第三电压施加到SRAM单元的反相器的接地电源节点，将互补位线之一预充电至全局接地电压，并且在对SRAM单元的写入操作期间将高于全局电源电压的第二电压施加到存取晶体管。

14. 发明申请

US20110305099A1 HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM 审中-公开
标题翻译：基于分层缓存的基于位线的SRAM
公开(公告)号：US20110305099A1
公开(公告)日：2011-12-15
申请号：US13105806
申请日：2011-05-11
申请人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryam Ashouei , Jos Huisken
发明人： Vibhu Sharma , Stefan Cosemans , Wim Dehaene , Francky Catthoor , Maryam Ashouei , Jos Huisken
IPC分类号： G11C7/12
CPC分类号： G11C11/419 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.
摘要翻译：公开了一种半导体存储器件。在一个方面，该设备包括具有连接到本地位线的存储器单元的存储器块，每个局部位线可连接到全局位线用于存储器读出。还存在用于对位线进行预充电的预充电电路和用于在读操作期间对全局位线进行放电的读缓冲器。本地位线被预充电到基本上低于存储器件的电源电压（VDD）的预定的第一电压。在每个本地位线和相应读缓冲器的输入节点之间提供段缓冲器。在连接的本地位线上发生放电时，段缓冲器在读操作期间激活读缓冲器。

15. 发明申请

US20110092834A1 ANALOGUE SIGNAL PROCESSORS 有权
标题翻译：模拟信号处理器
公开(公告)号：US20110092834A1
公开(公告)日：2011-04-21
申请号：US12882120
申请日：2010-09-14
申请人： Refet Firat YAZICIOGLU , Julien PENDERS , Sunyoung KIM
发明人： Refet Firat YAZICIOGLU , Julien PENDERS , Sunyoung KIM
IPC分类号： A61B5/0402
CPC分类号： A61B5/7225 , A61B5/04017 , A61B5/0402 , A61B5/0428 , A61B5/0476 , A61B5/0488 , A61B5/0531 , A61B5/7207 , A61B5/7221 , A61B5/7228 , A61B5/7232 , A61B5/7239 , G01R19/2509
摘要： An analogue signal processor (ASP) application-specific integrated circuit (ASIC) is disclosed. The ACIS can be used for remotely monitoring ECG signals of a subject that has reduced power consumption. In one aspect, the ASIC performs the functions of: ECG signal extraction with high resolution using ECG readout channel, feature extraction using a band-power extraction channel, adaptive sampling the ECG signals using an adaptive sampling analogue-to-digital converter, and impedance monitoring for signal integrity using an impedance monitoring channel. These functions enable the development of wireless ECG monitoring systems that have significantly lower power consumption but are more efficient that predecessor systems. In one embodiment, the ASP ASIC consumes 30 μW from a 2V supply with compression provided by adaptive sampling providing large reductions in power consumption of a wireless ECG monitoring system of which the ASP ASIC forms a part.
摘要翻译：公开了一种模拟信号处理器（ASP）专用集成电路（ASIC）。 ACIS可用于远程监控具有降低功耗的对象的ECG信号。在一个方面，ASIC执行以下功能：使用ECG读出通道具有高分辨率的ECG信号提取，使用带功率提取通道的特征提取，使用自适应采样模数转换器对ECG信号进行自适应采样，以及阻抗使用阻抗监测通道监测信号完整性。这些功能使得能够开发具有显着降低功耗的无线ECG监测系统，但是对于前一个系统而言更为有效。在一个实施例中，ASP ASIC从具有通过自适应采样提供的压缩的2V电源消耗30μW，从而大大降低了ASP ASIC形成的无线ECG监测系统的功耗。

16. 发明授权

US11576623B2 Method for generating a model for generating a synthetic ECG and a method and system for analysis of heart activity 有权
公开(公告)号：US11576623B2
公开(公告)日：2023-02-14
申请号：US16716991
申请日：2019-12-17
申请人： IMEC VZW , STICHTING IMEC NEDERLAND , REGENTS OF THE UNIVERSITY OF MINNESOTA
发明人： Dwaipayan Biswas , Luke Everson , Mario Konijnenburg , Christiaan Van Hoof , Nick Van Helleputte
IPC分类号： A61B5/024 , A61B5/327 , G06N3/04 , G06N3/08 , A61B5/00
摘要： A method of generating a model for generating a synthetic electrocardiography (ECG) signal comprises: receiving subject-specific training data for machine learning, said training data comprising a photoplethysmography (PPG) signal acquired from the subject and an ECG signal acquired from the subject, wherein the ECG signal provides a ground truth of the subject for associating the ECG signal with the PPG signal; using associated pairs of a time-series of the PPG signal and a corresponding time-series of the ECG signal as input to a deep neural network, DNN; and determining, through the DNN, a subject-specific model relating the PPG signal of the subject to the ECG signal of the subject for converting the PPG signal to a synthetic ECG signal using the subject-specific model.

17. 发明申请

US20220255554A1 ANALOG-TO-DIGITAL CONVERTER CIRCUITRY, AN INTEGRATED CIRCUIT DEVICE, A PHOTOPLETHYSMOGRAM DETECTOR, A WEARABLE DEVICE AND A METHOD FOR ANALOG-TO-DIGITAL CONVERSION 有权
公开(公告)号：US20220255554A1
公开(公告)日：2022-08-11
申请号：US17590211
申请日：2022-02-01
申请人： IMEC VZW , KATHOLIEKE UNIVERSITEIT LEUVEN , Stichting IMEC Nederland
发明人： Qiuyang LIN , Nick VAN HELLEPUTTE , Roland VAN WEGBERG , Shuang SONG
IPC分类号： H03M1/06
摘要： An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

18. 发明授权

US11350866B2 Read-out circuitry for acquiring a multi-channel biopotential signal and a sensor for sensing a biopotential signal 有权
公开(公告)号：US11350866B2
公开(公告)日：2022-06-07
申请号：US16710132
申请日：2019-12-11
申请人： STICHTING IMEC NEDERLAND , IMEC VZW
发明人： Roland Van Wegberg , Wim Sijbers
IPC分类号： A61B5/282 , A61B5/00 , H03F3/45 , A61B5/30
摘要： A read-out circuitry for acquiring a multi-channel biopotential signal, comprises: a plurality of read-out signal channels, each receiving an input signal from a unique signal electrode; a reference channel receiving a reference signal from a reference electrode; wherein each read-out signal channel and the reference channel comprises a channel amplifier connected to receive the input signal in a first input node and with an output node connected to a second input node via a channel feedback loop; wherein each signal channel amplifier comprises a capacitor between the second input nodes of the signal channel amplifier and the reference channel amplifier, and wherein each signal channel feedback loop and the reference channel feedback loop comprise a filter.

19. 发明申请

US20220100941A1 MEMORY DEVICE WITH PROGRAMMABLE CIRCUITRY 有权
公开(公告)号：US20220100941A1
公开(公告)日：2022-03-31
申请号：US17449383
申请日：2021-09-29
申请人： IMEC vzw , Stichting IMEC Nederland
发明人： Francky Catthoor , Jan Stuijt , Sandeep Pande
IPC分类号： G06F30/343
摘要： The present disclosure relates to a memory device comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory device to access data stored in the memory array in accordance with manifest loop instructions. The programmable circuitry comprises a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory device and to a processing system comprising the memory device.

20. 发明申请

US20220015712A1 Biosignal Monitoring System With Motion Artifact Reduction 有权
公开(公告)号：US20220015712A1
公开(公告)日：2022-01-20
申请号：US17376543
申请日：2021-07-15
申请人： IMEC VZW , Stichting IMEC Nederland
发明人： Roland Van Wegberg , Nick Van Helleputte
IPC分类号： A61B5/00 , A61B5/308 , A61B5/31 , A61B5/313
摘要： The disclosure includes a biosignal monitoring system for reducing a motion artifact from a biopotential electrical signal input, including a signal processing module, a motion artifact extraction module, and a subtraction module. The motion artifact extraction module and the signal processing module receive the biopotential electrical signal input and the subtraction module receives an extracted signal from an output of the motion artifact extraction module and a biopotential electrical signal from an output of the signal processing module. The subtraction module subtracts the extracted signal from the biopotential electrical signal. The motion artifact extraction module is an analog domain electronic circuit and includes a filter network configured for attenuating differential mode signals of the biopotential electrical signal input from a first frequency, and passing the motion artifact signal from the biopotential electrical signal input up to a second frequency at the output of the motion artifact extraction module.

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