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11. 发明申请

US20150179437A1 METHOD FOR MANUFACTURING A SILICON NITRIDE THIN FILM 有权
标题翻译：用于制造氮化硅薄膜的方法
公开(公告)号：US20150179437A1
公开(公告)日：2015-06-25
申请号：US14411999
申请日：2013-07-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Zhanxin Li
IPC分类号： H01L21/02
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/02211
摘要： A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 s. The above method for manufacturing a silicon nitride thin film provides a preferable parameter range and preferred parameters for generating a low-stress SIN thin film at low temperatures, achieves manufacture of a low-stress SIN thin film at low temperatures, and thus, better satisfies the situation requiring a low-stress SIN thin film.
摘要翻译：制造氮化硅薄膜的方法包括在低于350℃的环境温度下加入硅烷，氨气和氮气以产生和沉积氮化硅薄膜的步骤，其中填充硅烷的速率为300-350 sccm，氨气的加入速率为1000sccm，氮气的充填速度为1000sccm; 高频源的功率为0.15〜0.30KW，低频源的功率为0.15〜0.30KW; 反应压力为2.3〜2.6乇; 反应时间为4〜6秒。上述制造氮化硅薄膜的方法提供了优选的参数范围和用于在低温下产生低应力SIN薄膜的优选参数，在低温下实现了低应力SIN薄膜的制造，从而更好地满足需要低应力SIN薄膜的情况。

12. 发明申请

US20140329385A1 METHOD FOR MANUFACTURING SEMICONDUCTOR THICK METAL STRUCTURE 有权
标题翻译：制造半导体厚度金属结构的方法
公开(公告)号：US20140329385A1
公开(公告)日：2014-11-06
申请号：US14351828
申请日：2012-10-12
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD
发明人： Hsiao-Chia Wu , Shilin Fang , Tse-Huang Lo , Zhengpei Chen , Shu Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/7685 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76837 , H01L21/76838 , H01L24/03
摘要： A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.
摘要翻译：一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度的4μm金属凹凸结构。使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。

13. 发明授权

US08836419B2 PWM comparator and class D amplifier 有权
标题翻译： PWM比较器，D类放大器
公开(公告)号：US08836419B2
公开(公告)日：2014-09-16
申请号：US13807312
申请日：2011-12-07
申请人： Liang Cheng
发明人： Liang Cheng
IPC分类号： H03F3/38 , H03F3/217 , H03K5/24
CPC分类号： H03F3/217 , H03F2200/351 , H03K5/2481
摘要： The present disclosure generally relates to a PWM comparator and a class D amplifier. The PWM comparator described above introduces current feedback mechanism, basing the waveform state of received high frequency triangle signal and the level state of output signal of the PWM comparator, the hysteresis is changing dynamically. In the same resolution, the noise resistance ability of the PWM comparator described above is much better than that of the conventional PWM comparators which has a fixed hysteresis, thus the PWM comparator can work stably even if the duty cycle of output signal is nearly 100%.
摘要翻译：本公开一般涉及PWM比较器和D类放大器。上述PWM比较器引入电流反馈机制，根据接收的高频三角形信号的波形状态和PWM比较器的输出信号的电平状态，滞后动态变化。在相同的分辨率下，上述PWM比较器的抗噪声能力比具有固定滞后的常规PWM比较器的抗干扰能力好得多，因此即使输出信号的占空比接近100％，PWM比较器也能稳定工作。。

14. 发明申请

US20140145290A1 HIGH-VOLTAGE SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：高压肖特基二极管及其制造方法
公开(公告)号：US20140145290A1
公开(公告)日：2014-05-29
申请号：US14130449
申请日：2012-10-23
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Lihui Gu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/872
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/10 , H01L29/402 , H01L29/66143 , H01L29/872
摘要： A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.
摘要翻译：公开了一种高电压肖特基二极管及其制造方法。二极管包括：P型衬底和两个N型埋层，第一N型掩埋层位于阴极引出区下方，第二N型掩埋层位于阴极区下面; 外延层; 位于外延层上的两个N型阱区，第一N型阱区是横向漂移区，并具有阴极引出区，第二N型阱区位于第二N 型埋层，是阴极区; 位于所述第二N型掩埋层上并围绕所述阴极区的第一P型阱区; 位于所述横向漂移区上的场氧化物隔离区; 位于阴极区域的阳极和位于阴极引出区域的表面上的阴极。

15. 发明申请

US20130109146A1 METHOD FOR FABRICATING SMALL-SCALE MOS DEVICE 有权
标题翻译：用于制作小尺寸MOS器件的方法
公开(公告)号：US20130109146A1
公开(公告)日：2013-05-02
申请号：US13807306
申请日：2011-10-09
申请人： Le Wang
发明人： Le Wang
IPC分类号： H01L29/66
CPC分类号： H01L29/66492 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.
摘要翻译：一种制造小型MOS器件的方法，包括：制备衬底; 在所述栅极区域的第一侧沿所述衬底中形成第一沟槽，并且沿所述栅极区域的第二侧在所述衬底中形成第二沟槽，所述栅极区域的所述第一侧与所述栅极区域的第二侧相对; 在所述第一沟槽和所述第二沟槽中分别形成第一轻掺杂漏极区和第二轻掺杂漏极区; 在所述衬底中形成与所述第一轻掺杂漏极区域的至少第一部分重叠的第三沟槽和所述衬底中的与所述第二轻掺杂漏极区域的至少第一部分重叠的第四沟槽; 以及在第三沟槽和第四沟槽中分别形成源区和漏区。

16. 发明授权

US10816903B2 Photolithography method and system based on high step slope 有权
公开(公告)号：US10816903B2
公开(公告)日：2020-10-27
申请号：US15905969
申请日：2018-02-27
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Jiale Su
IPC分类号： G03F7/20 , G03F1/70 , G03F1/38
摘要： A photolithography system based on a high step slope may include a depositing unit configured to manufacture a sacrificial layer having high step slope on a substrate. The system may also include a coating unit configured to coat a photoresist layer on the sacrificial layer by performing a spin-on PR coating process to form a photolithographic layer. The system may further include a photolithography unit configured to perform one or more photolithography processes to the photolithographic layer. The photolithography unit may comprise a plurality of masks of compensation patterns. The compensation pattern may comprise a slope-top compensation pattern and a slope compensation pattern.

17. 发明授权

US10062746B2 Semiconductor rectifier and manufacturing method thereof 有权
公开(公告)号：US10062746B2
公开(公告)日：2018-08-28
申请号：US15539554
申请日：2015-09-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shengrong Zhong , Xiaoshe Deng , Dongfei Zhou
IPC分类号： H01L29/06 , H01L21/78 , H01L21/02 , H01L21/04 , H01L29/861 , H02M3/158 , H01L21/768
摘要： A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.

18. 发明授权

US09954431B2 Starting circuit of power management chip, and power management chip 有权
公开(公告)号：US09954431B2
公开(公告)日：2018-04-24
申请号：US14901482
申请日：2014-05-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Nan Zhang
IPC分类号： H02M1/36 , H02M1/00
CPC分类号： H02M1/36 , H02M2001/0006
摘要： A starting circuit (10) of a power management chip, comprising: a starting capacitor (C3) which is used for connecting a power supply via an external resistor (R2) to perform charging; a switch circuit (100) which is connected between the external resistor (R2) and the starting capacitor (C3); a voltage detection circuit (200) which is used for detecting a voltage on the starting capacitor (C3) and is connected to the switch circuit (100) so as to control the on/off switching of the switch circuit (100); and a voltage maintaining circuit (300) which is connected between the starting capacitor (C3) and an operating circuit of the power management chip and is used for acquiring a voltage that maintains the starting capacitor (C3) from the operating circuit of the power management chip, wherein when the voltage detection circuit (200) detects that the starting capacitor (C3) reaches the starting voltage of the power management chip, the broken circuit of the switch circuit (100) is controlled. Further provided is a power management chip including the above-mentioned starting circuit (10). Disconnecting an external power source from the starting capacitor after the operating circuit of the power management chip is started can reduce the electric energy consumption.

19. 发明授权

US09903884B2 Parallel plate capacitor and acceleration sensor comprising same 有权
公开(公告)号：US09903884B2
公开(公告)日：2018-02-27
申请号：US14435925
申请日：2013-08-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Meihan Guo , Xinwei Zhang , Changfeng Xia , Wei Su
IPC分类号： G01P15/125 , H02N1/08 , B81B7/02
CPC分类号： G01P15/125 , B81B7/02 , G01P2015/0837 , H01G5/16 , H02N1/08
摘要： A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

20. 发明授权

US09837532B2 Laterally diffused metal oxide semiconductor device and manufacturing method therefor 有权
公开(公告)号：US09837532B2
公开(公告)日：2017-12-05
申请号：US15119868
申请日：2015-05-04
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Guangsheng Zhang , Sen Zhang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

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