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    • 11. 发明授权
    • Thermochromic indicator materials with controlled reversibility
    • 热变色指示剂材料具有可控制的可逆性
    • US07517475B2
    • 2009-04-14
    • US11024326
    • 2004-12-28
    • Brett LuchtWilliam B. EulerYu Wang
    • Brett LuchtWilliam B. EulerYu Wang
    • G01N31/00G01N33/00
    • G01K11/16
    • A thermal indicator material which comprises a plurality of polythiophenes having a second low temperature color and a high temperature color. The polythiophenes are structured and arranged to exhibit a color change from the second low temperature color to the high temperature color when the thermal indicator material is exposed to a temperature that meets or exceeds a pre-determined temperature and to exhibit a color change from the high temperature color to a first low temperature color when the thermal indicator material is exposed to a decline in temperature from a temperature that meets or exceeds the predetermined temperature to a temperature of within the range of between about 5 to 20° C. below the pre-determined temperature that occurs in a time period of greater than 2.0 seconds.
    • 一种热指示剂材料,其包含具有第二低温颜色和高温颜色的多个聚噻吩。 聚噻吩被构造和布置成当热指示剂材料暴露于达到或超过预定温度的温度并且表现出从高的颜色变化时,从第二低温颜色到高温颜色的颜色变化 当热指示剂材料从达到或超过预定温度的温度暴露于温度下降到低于预定温度的约5至20℃之间的温度时,将温度颜色变为第一低温颜色, 在大于2.0秒的时间段内发生的确定的温度。
    • 12. 发明申请
    • SCSI-to-IP Cache Storage Device and Method
    • SCSI到IP缓存存储设备和方法
    • US20080010411A1
    • 2008-01-10
    • US11857319
    • 2007-09-18
    • Qing YangXubin He
    • Qing YangXubin He
    • G06F12/00
    • G06F12/0866G06F3/061G06F3/0656G06F3/067
    • A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface (40) that facilitates system communications with a host computing device or the storage unit, and a Ethernet interface (42) that allows the system to receive data from and send data to the Internet. The cache storage system further comprises a processing unit (44) that includes a processor (46), a memory (48) and a log disk (52) configured as a sequential access device. The log disk (52) caches data along with the memory (48) resident in the processing unit (44), wherein the log disk (52) and the memory (48) are configured as a two-level hierarchical cache.
    • SCSI到IP高速缓存存储系统将主机计算设备或存储单元互连到交换分组网络。 高速缓存存储系统包括便于与主机计算设备或存储单元的系统通信的SCSI接口(40),以及允许系统从Internet接收数据和向因特网发送数据的以太网接口(42)。 高速缓存存储系统还包括处理单元(44),其包括处理器(46),配置为顺序存取设备的存储器(48)和日志盘(52)。 日志盘(52)与驻留在处理单元(44)中的存储器(48)一起缓存数据,其中日志盘(52)和存储器(48)被配置为两级分层高速缓存。
    • 19. 发明授权
    • Signal processing apparatus for generating a fourier transform
    • 用于生成傅里叶变换的信号处理装置
    • US4999799A
    • 1991-03-12
    • US295122
    • 1989-01-09
    • Donald W. Tufts
    • Donald W. Tufts
    • G06F17/14G06G7/186G06J1/00
    • G06F17/14G06G7/1865G06J1/005
    • Apparatus for producing the Fourier coefficients of a time and/or space-varying input signal utilizes a bank of delay filters whose outputs are selectively connected to the inputs of a bank of accumulating circuit each of which produces one of the desired Fourier coefficients. Each of the delay filters produces an output signal which is the weighted average of one or more samples of the input signal, the samples being equally spaced in time over the period of the input signal. The accumulating circuits, equal in number to the number of harmonics in the desired Fourier series, each produce a weighted sum of the output(s) of selected delay filters which are interconnected with the accumulating circuits in accordance with the so-called Mobius function. The apparatus may employ either general purpose or special purpose digital or analog processing circuits, and is particularly suitable for implementation with VLSI fabrication techniques. Futher circuit simplification may be achieved by preprocessing the input signal into a delta modulated bipolar signal to reduce the number of internal data paths and to permit the signal averaging function to be implemented with a simple up-down counter.
    • 用于产生时间和/或空间变化输入信号的傅里叶系数的装置利用一组延迟滤波器,其输出选择性地连接到一组累加电路的输入端,每个输出电路产生期望的傅里叶系数之一。 每个延迟滤波器产生输出信号,该输出信号是输入信号的一个或多个样本的加权平均值,样本在输入信号的周期内等时间间隔。 与期望的傅立叶级数中的谐波数量相等的累积电路各自产生根据所谓的莫比乌斯(Mobius)功能与累积电路互连的所选择的延迟滤波器的输出的加权和。 该装置可以采用通用或专用数字或模拟处理电路,并且特别适用于利用VLSI制造技术的实现。 可以通过将输入信号预处理为增量调制双极信号来减少内部数据路径的数量并允许使用简单的升降计数器来实现信号平均功能来实现更好的电路简化。