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11. 发明申请

US20150054555A1 SELF-BIASED DELAY LOCKED LOOP WITH DELAY LINEARIZATION 有权
标题翻译：具有延迟线性化的自锁延迟锁定环
公开(公告)号：US20150054555A1
公开(公告)日：2015-02-26
申请号：US14387618
申请日：2012-04-26
申请人： Daniel A. Berkram , Zhubiao Zhu
发明人： Daniel A. Berkram , Zhubiao Zhu
IPC分类号： H03L7/091 , H03L7/107 , H03L7/093
CPC分类号： H03L7/091 , H03K5/135 , H03L7/0812 , H03L7/093 , H03L7/1075 , H03L2207/04
摘要： Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DU) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (188, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 206) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal. The DAC bias circuit (122, 222, 422) configured to adjust the feedback signal to cause the delayed clock signal at the output of the DAC (106, 206, 306) to be non-linear to counteract non-linear delay characteristics of the DCC (109, 209).
摘要翻译：提供了具有延迟线性化的自偏置延迟看法循环的装置和方法。一个示例的延迟锁定环路（DU）电路（100,200）可以包括数模转换器（DAC）（104,204,304）和通信地耦合到DAC的输出的偏置发生器（188,208）（106,206,306）。偏置发生器（108,206）被配置为提供时钟信号和偏置信号。延迟控制电路（DCC）（109,209）通信地耦合到偏置发生器（108,208）。 DCC（109,209）被配置为基于时钟信号和偏置信号提供延迟的时钟信号。 DAC偏置电路（122,222,422）通信地耦合到DAC（106,206,306），并且被配置为基于偏置信号向DAC（104,204,304）提供反馈信号。所述DAC偏置电路（122,222,422）被配置为调整所述反馈信号以使所述DAC（106,206,306）的输出处的所述经延迟的时钟信号是非线性的，以抵消所述DAC的非线性延迟特性 DCC（109,209）。

12. 发明申请

US20080101513A1 Systems and methods for synchronizing an input signal 有权
标题翻译：用于同步输入信号的系统和方法
公开(公告)号：US20080101513A1
公开(公告)日：2008-05-01
申请号：US11588459
申请日：2006-10-27
申请人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
发明人： Zhubiao Zhu , Carson Donahue Henrion , Daniel Alan Berkram
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H03K3/0375 , H03K3/35613 , H03K5/135
摘要： Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
摘要翻译：提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。一个实施例包括一种系统，其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出作为第一输出信号的延迟版本的延迟信号的延迟元件。该系统还包括一个通过栅极元件，配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。第二输出信号具有延迟的输入边沿，而没有延迟的分辨率边缘。响应于具有亚稳态的第一输出信号，该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。

13. 发明授权

US09300304B2 Self-biased delay locked loop with delay linearization 有权
标题翻译：具有延迟线性化的自偏置延迟锁定环
公开(公告)号：US09300304B2
公开(公告)日：2016-03-29
申请号：US14387618
申请日：2012-04-26
申请人： Daniel A. Berkram , Zhubiao Zhu
发明人： Daniel A. Berkram , Zhubiao Zhu
IPC分类号： H03L7/00 , H03L7/091 , H03L7/081 , H03L7/093 , H03L7/107 , H03K5/135
CPC分类号： H03L7/091 , H03K5/135 , H03L7/0812 , H03L7/093 , H03L7/1075 , H03L2207/04
摘要： Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DLL) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (108, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 208) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal. The DAC bias circuit (122, 222, 422) is configured to adjust the feedback signal to cause the delayed clock signal at the output of the DAC (106, 206, 306) to be non-linear to counteract non-linear delay characteristics of the DCC (109, 209).
摘要翻译：提供了具有延迟线性化的自偏置延迟看法循环的装置和方法。一个示例性延迟锁定环（DLL）电路（100,200）可以包括数模转换器（DAC）（104,204,304）和通信地耦合到DAC的输出的偏置发生器（108,208）（106,206,306）。偏置发生器（108,208）被配置为提供时钟信号和偏置信号。延迟控制电路（DCC）（109,209）通信地耦合到偏置发生器（108,208）。 DCC（109,209）被配置为基于时钟信号和偏置信号提供延迟的时钟信号。 DAC偏置电路（122,222,422）通信地耦合到DAC（106,206,306），并且被配置为基于偏置信号向DAC（104,204,304）提供反馈信号。 DAC偏置电路（122,222,422）被配置为调整反馈信号以使得DAC（106,206,306）的输出处的延迟的时钟信号是非线性的，以抵消非线性延迟特性 DCC（109,209）。

14. 发明授权

US07134097B2 Method and apparatus for a configurable metal register 失效
标题翻译：可配置金属寄存器的方法和装置
公开(公告)号：US07134097B2
公开(公告)日：2006-11-07
申请号：US10383120
申请日：2003-03-06
申请人： Zhubiao Zhu , Hong Jiang , John R. Spencer , Michael A Buckley
发明人： Zhubiao Zhu , Hong Jiang , John R. Spencer , Michael A Buckley
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C2029/0403
摘要： A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.
摘要翻译：集成电路的可配置金属寄存器，允许通过更改寄存器的金属图形解决方案中的任何金属或任何触点来更改寄存器输出值。可以改变金属图案溶液中的多于一个金属和/或相应的接触，从而相应地改变寄存器输出值。

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