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11. 发明授权

US07723790B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07723790B2
公开(公告)日：2010-05-25
申请号：US12208840
申请日：2008-09-11
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/00
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

12. 发明申请

US20090014797A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090014797A1
公开(公告)日：2009-01-15
申请号：US12208840
申请日：2008-09-11
申请人： Yuuichi HIRANO , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi HIRANO , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L29/786
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

13. 发明申请

US20070138560A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070138560A1
公开(公告)日：2007-06-21
申请号：US11677956
申请日：2007-02-22
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/12 , H01L29/94
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

14. 发明授权

US07193272B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07193272B2
公开(公告)日：2007-03-20
申请号：US11108843
申请日：2005-04-19
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

15. 发明授权

US06958266B2 Semiconductor device, method of manufacturing same and method of designing same 有权
公开(公告)号：US06958266B2
公开(公告)日：2005-10-25
申请号：US10120485
申请日：2002-04-12
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

16. 发明授权

US06611041B2 Inductor with patterned ground shield 有权
公开(公告)号：US06611041B2
公开(公告)日：2003-08-26
申请号：US10207233
申请日：2002-07-30
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
IPC分类号： H01L2900
CPC分类号： H01L23/5227 , H01L21/28518 , H01L21/84 , H01L23/645 , H01L27/0688 , H01L27/08 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

17. 发明授权

US06563172B2 Semiconductor substrate processing method 失效
公开(公告)号：US06563172B2
公开(公告)日：2003-05-13
申请号：US09770388
申请日：2001-01-29
申请人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L2701
CPC分类号： H01L21/7624 , H01L21/3105 , H01L21/31155
摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

18. 发明授权

US06436792B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06436792B1
公开(公告)日：2002-08-20
申请号：US09325644
申请日：1999-06-04
申请人： Yasuo Yamaguchi , Shigenobu Maeda , Yuuichi Hirano
发明人： Yasuo Yamaguchi , Shigenobu Maeda , Yuuichi Hirano
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76291
摘要： A silicon oxide film (6aa) is formed on an upper surface of an SOI layer (3), a silicon nitride film (6bb) is formed on the silicon oxide film (6aa), and a silicon oxide film (6cc) is formed on the silicon nitride film (6bb). Using the silicon nitride film (6bb) as an etch stopper, anisotropic dry etching is performed on the silicon oxide film (6cc) in first and second device formation regions. Then, using the silicon oxide film (6aa) as an etch stopper, anisotropic dry etching is performed on the silicon nitride film (6bb) in the first and second device formation regions. The silicon oxide film (6aa) in the first and second device formation regions is removed by wet etching using hydrofluoric acid to expose the upper surface of the SOI layer (3). A method of manufacturing a semiconductor device is provided which is capable of avoiding the formation of a damaged layer in a main surface of an SOI substrate when such a device isolation structure is formed.
摘要翻译：在SOI层（3）的上表面上形成氧化硅膜（6aa），在氧化硅膜（6aa）上形成氮化硅膜（6bb），在氧化硅膜（6a）上形成氧化硅膜（6cc）氮化硅膜（6bb）。使用氮化硅膜（6bb）作为蚀刻停止层，对第一和第二器件形成区域中的氧化硅膜（6cc）进行各向异性干蚀刻。然后，使用氧化硅膜（6aa）作为蚀刻停止层，对第一和第二器件形成区域中的氮化硅膜（6bb）进行各向异性干蚀刻。通过使用氢氟酸的湿蚀刻除去第一和第二器件形成区域中的氧化硅膜（6aa），以暴露SOI层（3）的上表面。提供一种制造半导体器件的方法，其能够避免在形成器件隔离结构时在SOI衬底的主表面中形成受损层。

19. 发明授权

US06232201B1 Semiconductor substrate processing method 失效
标题翻译：半导体衬底处理方法
公开(公告)号：US06232201B1
公开(公告)日：2001-05-15
申请号：US09113155
申请日：1998-07-10
申请人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L2176
CPC分类号： H01L21/7624 , H01L21/3105 , H01L21/31155
摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.
摘要翻译：目的在于提供一种半导体衬底处理方法以及防止从衬底的边缘部分形成微粒的半导体衬底。在SOI衬底（10）的半径方向上将硅离子注入到SOI衬底（10）的边缘部分中，以使SOI衬底（10）的边缘部分中的掩埋氧化膜（2）成为硅丰富的状态。因此，提供SOI衬底（100），其中掩埋氧化膜（2）在边缘部分中基本上被去除。

20. 发明授权

US06872979B2 Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers 失效
标题翻译：具有层叠氧化物的半导体衬底和在层叠层的边缘上形成有熔融或外延层的SOI层
公开(公告)号：US06872979B2
公开(公告)日：2005-03-29
申请号：US10357392
申请日：2003-02-04
申请人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L21/265 , H01L21/02 , H01L21/3105 , H01L21/3115 , H01L21/762 , H01L27/12 , H01L21/76
CPC分类号： H01L21/7624 , H01L21/3105 , H01L21/31155
摘要： A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.
摘要翻译：一种半导体衬底，其防止从衬底的边缘部分形成颗粒。衬底包含衬底上氧化物膜和堆叠在氧化物膜上的SOI层。通过混合SOI层和基板上氧化物膜以覆盖边缘部分，在衬底上氧化膜和SOI层的边缘部分上形成熔融层。也可以在衬底上氧化膜的边缘部分和SOI层上形成外延层以覆盖边缘部分。

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