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    • 13. 发明授权
    • Semiconductor memory device with delay in address predecoder circuit
independent from ATD
    • 具有独立于ATD的地址预解码器电路延迟的半导体存储器件
    • US5062082A
    • 1991-10-29
    • US642746
    • 1991-01-18
    • Yun-ho Choi
    • Yun-ho Choi
    • G11C11/41G11C8/18G11C11/413
    • G11C8/18
    • A semiconductor memory device includes an address transition detection circuit for detecting the state transition of address signals and generating a pulse having a predetermined pulse width, a precharge circuit for generating and equalizing a pair of input/output lines in response to the output pulse of the address transition detection circuit, address decoder circuit for decoding the address signals and generating an address selection signal, and a gate circuit connecting the pair of input/output lines to a selected pair of bit lines in response to the address selection signal of the address decoder circuit. In the device, the address decoder circuit has a signal delay characteristic for delaying signals from the state transition of the address signal until the completion of the precharge and equalization of the I/O lines. Accordingly, the access time of the memory address can be operated in high speed by forming the address decoder independent of an ATD pulse, and the circuit can be easily designed and the cost can be saved by eliminating the wiring between the ATD circuit and the address decoder.
    • 半导体存储器件包括地址转换检测电路,用于检测地址信号的状态转换并产生具有预定脉冲宽度的脉冲;预充电电路,用于响应于输出脉冲的输出脉冲产生和均衡一对输入/输出线 地址转换检测电路,用于对地址信号进行解码并产生地址选择信号的地址解码器电路;以及门电路,响应于地址解码器的地址选择信号,将一对输入/输出线连接到所选择的一对位线 电路。 在设备中,地址解码器电路具有用于将来自地址信号的状态转换的信号延迟到I / O线的预充电和均衡之前的信号延迟特性。 因此,存储器地址的访问时间可以通过独立于ATD脉冲形成地址解码器而高速运行,并且可以容易地设计电路,并且可以通过消除ATD电路和地址之间的布线来节省成本 解码器。
    • 18. 发明授权
    • Data output buffer with selective bootstrap circuit
    • 具有选择性自举电路的数据输出缓冲器
    • US5270588A
    • 1993-12-14
    • US813451
    • 1991-12-26
    • Yun-ho Choi
    • Yun-ho Choi
    • G11C7/10H03K19/017H03K19/092H03K19/02
    • G11C7/1057G11C7/1051G11C7/106H03K19/01714H03K19/01721
    • A data output buffer includes an output driving stage having a pair of parallel pull-up transistors and a pull-down transistor, a latch circuit for latching a pair of complementary signals, a second gate for gating the non-inverted output signal of the latch circuit in response to an external output enable signal and then supplying it to the gate of one pull-up transistor of the output driving state, a third gate also for gating the non-inverted output signal of the latch circuit in response to an external output enable signal, and a selective bootstrap circuit for driving the other pull-up transistor of the output driving stage. The output driving stage is driven to an external supply voltage when the external supply voltage is higher than a set voltage, and is driven to a boosted voltage when the external supply voltage is lower than the set voltage, determined by output signals from the second and third gates.
    • 数据输出缓冲器包括具有一对并行上拉晶体管和下拉晶体管的输出驱动级,用于锁存一对互补信号的锁存电路,用于选通锁存器的非反相输出信号的第二门 电路,响应于外部输出使能信号,然后将其提供给输出驱动状态的一个上拉晶体管的栅极,第三栅极还用于响应于外部输出门控锁存电路的非反相输出信号 使能信号和用于驱动输出驱动级的另一个上拉晶体管的选择性自举电路。 当外部电源电压高于设定电压时,输出驱动级被驱动到外部电源电压,并且当外部电源电压低于由第二和第二输出信号确定的设定电压时被驱动到升压电压 第三门。
    • 19. 发明授权
    • Output feedback control circuit for integrated circuit device
    • 集成电路器件的输出反馈控制电路
    • US5015891A
    • 1991-05-14
    • US407756
    • 1989-09-15
    • Yun-ho Choi
    • Yun-ho Choi
    • G11C11/417G11C7/06G11C11/40G11C11/407G11C11/409
    • G11C7/062
    • An output feedback control circuit for an integrated circuit (IC) device is disclosed which includes an I/O line sense amplifier for amplifying the weak signals read out from cells, a read driver for amplifying the output of the I/O line sense amplifier, an output latch/transmission block for latching or transmitting the output signals of the read driver, a precharge block for precharging the output node of the output latch/transmission block, and a state transition detecting block for generating feedback control clocks. If the circuit of the present invention is installed to the output terminal of an IC decive, the data latched at the output node can be maintained regardless of the intruding of an external noise until a precharge clock is generated at a new cycle. Further, the sense amplifier and the read driver are disabled after having amplified the input signals within a single cycle, and therefore, the DC power consumption can be prevented.
    • 公开了一种用于集成电路(IC)装置的输出反馈控制电路,其包括用于放大从单元读出的弱信号的I / O线读出放大器,用于放大I / O线读出放大器的输出的读驱动器, 用于锁存或发送读驱动器的输出信号的输出锁存/发送块,用于对输出锁存/发送块的输出节点进行预充电的预充电块,以及用于产生反馈控制时钟的状态转移检测块。 如果将本发明的电路安装到IC的输出端,则可以保持在输出节点处锁存的数据,而不管侵入外部噪声,直到在新周期产生预充电时钟。 此外,在单个周期中放大输入信号之后,读出放大器和读取驱动器被禁止,因此可以防止DC功率消耗。