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    • 12. 发明授权
    • Address management apparatus and address management method
    • 地址管理装置和地址管理方法
    • US07050433B2
    • 2006-05-23
    • US09754142
    • 2001-01-05
    • Satoshi AndoYuji ShimizuKazuhide Sawabe
    • Satoshi AndoYuji ShimizuKazuhide Sawabe
    • H04L12/28
    • H04L61/20H04L29/12009H04L29/12018H04L29/12207H04L61/10
    • An address management apparatus includes a storage unit for storing a table showing the correspondence between data link layer and network layer addresses, a first search unit for searching the table for an unused data link layer address, a second search unit for searching the table for a network layer address corresponding to a specified data link layer address, and an instruction unit for transmitting an instruction including the unused data link layer address to a terminal specified by the detected network layer address. The apparatus also includes an updation unit for updating the correspondence between the data link layer and the network layer addresses on the table according to the instruction, a detection unit for detecting the instruction to obtain the data link layer address, and a setting unit for setting the data link layer address obtained by the detection unit in the self terminal.
    • 地址管理装置包括存储单元,用于存储表示数据链路层与网络层地址之间的对应关系的表,第一搜索单元,用于在表中搜索未使用的数据链路层地址;第二搜索单元,用于搜索表中的 网络层地址对应于指定的数据链路层地址,以及指令单元,用于将包括未使用的数据链路层地址的指令发送到由检测到的网络层地址指定的终端。 该装置还包括更新单元,用于根据指令更新数据链路层和表上的网络层地址之间的对应关系;检测单元,用于检测获取数据链路层地址的指令;以及设置单元,用于设置 由自身终端中的检测单元获得的数据链路层地址。
    • 17. 发明申请
    • Semiconductor device and method for producing the same
    • 半导体装置及其制造方法
    • US20060035468A1
    • 2006-02-16
    • US11249908
    • 2005-10-12
    • Satoshi Ando
    • Satoshi Ando
    • H01L21/302H01L21/461
    • H01L21/0332H01L21/31116H01L21/32136H01L21/32138H01L21/32139H01L21/76834H01L21/76838H01L21/76885
    • The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.
    • 本发明提供一种半导体器件,即使在具有需要在较长时间的蚀刻时间内进行图案化的布线层的情况下,图案化的布线层的形状的缺陷也较少,及其制造方法。 通过使用用作掩模的光致抗蚀剂17a的氟基气体进行干法蚀刻,通过对绝缘膜进行图案化来形成辅助掩模15a。 接下来,通过使用辅助掩模15a和剩余的光致抗蚀剂17a进行使用氯基气体的干蚀刻作为掩模,通过图案化布线层13形成布线13a。在第二蚀刻中,辅助掩模15a 几乎没有蚀刻。 因此,如果光致抗蚀剂17a的厚度与现有技术相同,则可以对现有技术中的较厚布线层13进行图案化。
    • 19. 发明授权
    • Wiring with insulation pattern
    • 接线绝缘图案
    • US06794758B2
    • 2004-09-21
    • US10268626
    • 2002-10-10
    • Satoshi Ando
    • Satoshi Ando
    • H01L23152
    • H01L21/0332H01L21/31116H01L21/32136H01L21/32138H01L21/32139H01L21/76834H01L21/76838H01L21/76885
    • The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.
    • 本发明提供一种半导体器件,即使在具有需要在较长时间的蚀刻时间内进行图案化的布线层的情况下,图案化的布线层的形状的缺陷也较少,及其制造方法。 通过用作为掩模的光致抗蚀剂17a的氟基气体进行干蚀刻,通过图案化绝缘膜形成辅助掩模15a。 接下来,通过使用辅助掩模15a和剩余的光致抗蚀剂17a作为掩模使用氯基气体进行干法蚀刻,通过图案化布线层13形成布线13a。在第二蚀刻中,辅助掩模15a几乎不被蚀刻。 因此,如果光致抗蚀剂17a的厚度等同于现有技术的厚度,则可以对现有技术中较厚的布线层13进行图案化。